公开(公告)号：US08352685B2

公开(公告)日：2013-01-08

申请号：US12860505

申请日：2010-08-20

Applicant: Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0891 ,  G06F12/0804

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为折叠。 折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

公开(公告)号：US08301843B2

公开(公告)日：2012-10-30

申请号：US12650075

申请日：2009-12-30

Applicant: Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

Inventor： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0808 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0815 ,  G06F2212/507

Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract translation: 在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。 核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。 如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。 另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。 第二个交易与第一笔交易不同。 例如，第二事务可以是无效事务，并且第一事务可以是探查事务。 在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

公开(公告)号：US20120047332A1

公开(公告)日：2012-02-23

申请号：US12860505

申请日：2010-08-20

Applicant: Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

IPC: G06F12/08 ,  G06F3/00 ,  G06F12/00

CPC classification number: G06F12/0891 ,  G06F12/0804

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。折叠的写入缓冲器条目及其中的折叠的写入操作可以包括至少一个写入操作，该写入操作已覆盖由 以前的写入操作在缓冲区条目中。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

公开(公告)号：US07707361B2

公开(公告)日：2010-04-27

申请号：US11281840

申请日：2005-11-17

Applicant: Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

Inventor： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0808 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0815 ,  G06F2212/507

Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract translation: 在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。 核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。 如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。 另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。 第二个交易与第一笔交易不同。 例如，第二事务可以是无效事务，并且第一事务可以是探查事务。 在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

公开(公告)号：US6047357A

公开(公告)日：2000-04-04

申请号：US379048

申请日：1995-01-27

Applicant: Peter J. Bannon ,  Elizabeth M. Cooper

Inventor： Peter J. Bannon ,  Elizabeth M. Cooper

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F2212/601

Abstract: A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.

Abstract translation: 高速缓冲存储器系统包括以分层方式布置的多个高速缓存级别。 存储在较高级别高速缓存级别的数据项目也存储在所有较低级别的高速缓存中。 在较高级别的缓存的初始查找期间检测到最新版本的数据项。 较高级别高速缓存的初始查找包括下一级较低级缓存的地址位的比较。 因此，能够检测数据项的最新版本，而无需对下一级缓存进行附加查找。

公开(公告)号：US09280352B2

公开(公告)日：2016-03-08

申请号：US13307969

申请日：2011-11-30

Applicant: Ramesh B. Gunna ,  Peter J. Bannon ,  Rajat Goel

Inventor： Ramesh B. Gunna ,  Peter J. Bannon ,  Rajat Goel

IPC: G06F9/22 ,  G06F9/28 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3814

Abstract: An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.

Abstract translation: 一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。 先行指针扫描调度队列的最新条目以获取微代码指令。 检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。 然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

公开(公告)号：US20120290818A1

公开(公告)日：2012-11-15

申请号：US13557725

申请日：2012-07-25

Applicant: Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

Inventor： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract translation: 在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。 其他依赖关系在第二个依赖关系数组中被跟踪。 第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。 第二个数组可能比第一个依赖数组慢得多。

公开(公告)号：US08285937B2

公开(公告)日：2012-10-09

申请号：US12711941

申请日：2010-02-24

Applicant: Peter J. Bannon ,  Po-Yung Chang

Inventor： Peter J. Bannon ,  Po-Yung Chang

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/522 ,  G06F9/526 ,  G06F2209/521

Abstract: In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.

Abstract translation: 在一个实施例中，处理器可以被配置为在由处理器执行的推测性指令流中检测存储排他操作，随后进行存储器障碍操作。 处理器可以融合存储专有操作和存储器屏障操作，创建融合操作。 可以传输和全局排序融合操作，并且响应于融合操作，处理器可以完成存储排他操作和存储器屏障操作两者。 当融合操作通过处理器和一个或多个其它组件（例如高速缓存层级中的高速缓存）进行到系统中的订购点时，融合操作可以推动先前的存储器操作来实现存储器屏障操作。 在一些实施例中，如果存储排他操作在订购点成功，则可以减少完成存储排他操作和后续数据存储器屏障操作的等待时间。

公开(公告)号：US20110208915A1

公开(公告)日：2011-08-25

申请号：US12711941

申请日：2010-02-24

Applicant: Peter J. Bannon ,  Po-Yung Chang

Inventor： Peter J. Bannon ,  Po-Yung Chang

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/522 ,  G06F9/526 ,  G06F2209/521

Abstract: In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.

Abstract translation: 在一个实施例中，处理器可以被配置为在由处理器执行的推测性指令流中检测存储排他操作，随后进行存储器障碍操作。 处理器可以融合存储专有操作和存储器屏障操作，创建融合操作。 可以传输和全局排序融合操作，并且响应于融合操作，处理器可以完成存储排他操作和存储器屏障操作两者。 当融合操作通过处理器和一个或多个其它组件（例如高速缓存层级中的高速缓存）进行到系统中的订购点时，融合操作可以推动先前的存储器操作来实现存储器屏障操作。 在一些实施例中，如果存储排他操作在订购点成功，则可以减少完成存储排他操作和后续数据存储器屏障操作的等待时间。

公开(公告)号：US06546453B1

公开(公告)日：2003-04-08

申请号：US09653093

申请日：2000-08-31

Applicant: Richard E. Kessler ,  Maurice B. Steinman ,  Peter J. Bannon ,  Michael C. Braganza ,  Gregg A. Bouchard

Inventor： Richard E. Kessler ,  Maurice B. Steinman ,  Peter J. Bannon ,  Michael C. Braganza ,  Gregg A. Bouchard

IPC: G06F1200

CPC classification number: G06F12/0882 ,  G06F12/0215 ,  G06F12/0607

Abstract: A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield. This diminishes page misses caused by replacement of data blocks from the cache memory because the read of the new data block and write of the victim data block are not to the same memory bank. Adjacent memory bank conflicts are reduced for sequential accesses to memory banks by reversing the bit order of a bank number subfield within the bank subfield of the device address.

Abstract translation: 计算机系统包含包括软件可编程存储器映射器的处理器。 存储器映射器将由处理器生成的地址映射到用于访问物理主存储器的设备地址。 处理器还包括将处理器地址映射到高速缓存地址的高速缓存控制器。 高速缓存地址使用索引子字段将主存储器的数据块放入存储器高速缓存。 物理主存储器包含RDRAM设备，每个RDRAM设备包含存储行和数据列的多个存储器组。 内存映射器将处理器地址映射到设备地址，以提高内存系统性能。 该映射最小化了存储体之间的存储器访问冲突。 通过将对应于银行子字段的多个位放置在索引子字段的最高有效边界位之上来减少存储体之间的冲突。 由于新数据块的读取和受害者数据块的写入不是同一个存储体，这会减少由高速缓冲存储器替换数据块所造成的页面错误。 通过反转设备地址的银行子字段内的库号子字段的位顺序，减少了对存储体的顺序访问的相邻存储体冲突。