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    Efficient handling of misaligned loads and stores
    1.
    发明授权
    Efficient handling of misaligned loads and stores 有权
    高效处理不对齐的负载和商店

    公开(公告)号：US09131899B2

    公开(公告)日：2015-09-15

    申请号：US13177192

    申请日：2011-07-06

    Applicant: Hari S. Kannan ,  Pradeep Kanapathipillai ,  Greg M. Hess

    Inventor： Hari S. Kannan ,  Pradeep Kanapathipillai ,  Greg M. Hess

    IPC: G06F12/00 ,  A61B5/00 ,  A61B5/053 ,  A61N1/05 ,  A61N1/362 ,  G06F12/08

    CPC classification number: A61B5/686 ,  A61B5/0538 ,  A61B5/4836 ,  A61B5/7275 ,  A61N1/05 ,  A61N1/362 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/0877

    Abstract: A system and method for efficiently handling misaligned memory accesses within a processor. A processor comprises a load-store unit (LSU) with a banked data cache (d-cache) and a banked store queue. The processor generates a first address corresponding to a memory access instruction identifying a first cache line. The processor determines the memory access is misaligned which crosses over a cache line boundary. The processor generates a second address identifying a second cache line logically adjacent to the first cache line. If the instruction is a load instruction, the LSU simultaneously accesses the d-cache and store queue with the first and the second addresses. If there are two hits, the data from the two cache lines are simultaneously read out. If the access is a store instruction, the LSU separates associated write data into two subsets and simultaneously stores these subsets in separate cache lines in separate banks of the store queue.

    Abstract translation: 一种用于有效地处理处理器内的未对准存储器访问的系统和方法。 处理器包括具有分组数据高速缓存（d-cache）和分组存储队列的加载存储单元（LSU）。 处理器产生对应于识别第一高速缓存行的存储器访问指令的第一地址。 处理器确定在高速缓存线边界上跨越的存储器访问未对准。 处理器生成标识逻辑上与第一高速缓存线相邻的第二高速缓存线的第二地址。 如果指令是加载指令，则LSU同时访问d-cache并存储具有第一和第二地址的队列。 如果有两个命中，则同时读出来自两条缓存行的数据。 如果访问是存储指令，则LSU将相关联的写入数据分成两个子集，并且将这些子集同时存储在存储队列的单独的存储区中的单独的高速缓存行中。

    EFFICIENT HANDLING OF MISALIGNED LOADS AND STORES
    2.
    发明申请
    EFFICIENT HANDLING OF MISALIGNED LOADS AND STORES 有权
    有效处理缺陷货物和仓库

    公开(公告)号：US20130013862A1

    公开(公告)日：2013-01-10

    申请号：US13177192

    申请日：2011-07-06

    Applicant: Hari S. Kannan ,  Pradeep Kanapathipillai ,  Greg M. Hess

    Inventor： Hari S. Kannan ,  Pradeep Kanapathipillai ,  Greg M. Hess

    IPC: G06F12/08

    CPC classification number: A61B5/686 ,  A61B5/0538 ,  A61B5/4836 ,  A61B5/7275 ,  A61N1/05 ,  A61N1/362 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/0877

    Abstract: A system and method for efficiently handling misaligned memory accesses within a processor. A processor comprises a load-store unit (LSU) with a banked data cache (d-cache) and a banked store queue. The processor generates a first address corresponding to a memory access instruction identifying a first cache line. The processor determines the memory access is misaligned which crosses over a cache line boundary. The processor generates a second address identifying a second cache line logically adjacent to the first cache line. If the instruction is a load instruction, the LSU simultaneously accesses the d-cache and store queue with the first and the second addresses. If there are two hits, the data from the two cache lines are simultaneously read out. If the access is a store instruction, the LSU separates associated write data into two subsets and simultaneously stores these subsets in separate cache lines in separate banks of the store queue.

    Abstract translation: 一种用于有效地处理处理器内的未对准存储器访问的系统和方法。 处理器包括具有分组数据高速缓存（d-cache）和分组存储队列的加载存储单元（LSU）。 处理器产生对应于识别第一高速缓存行的存储器访问指令的第一地址。 处理器确定在高速缓存线边界上跨越的存储器访问未对准。 处理器生成标识逻辑上与第一高速缓存线相邻的第二高速缓存线的第二地址。 如果指令是加载指令，则LSU同时访问d-cache并存储具有第一和第二地址的队列。 如果有两个命中，则同时读出来自两条缓存行的数据。 如果访问是存储指令，则LSU将相关联的写入数据分成两个子集，并且将这些子集同时存储在存储队列的单独的存储区中的单独的高速缓存行中。

    Split Scheduler
    7.
    发明申请
    Split Scheduler 有权
    拆分计划程序

    公开(公告)号：US20100162262A1

    公开(公告)日：2010-06-24

    申请号：US12338769

    申请日：2008-12-18

    Applicant: Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

    Inventor： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

    IPC: G06F9/46

    CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

    Abstract translation: 在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。 其他依赖关系在第二个依赖关系数组中被跟踪。 第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。 第二个数组可能比第一个依赖数组慢得多。

    Split Scheduler
    8.
    发明申请
    Split Scheduler 有权
    拆分计划程序

    公开(公告)号：US20120290818A1

    公开(公告)日：2012-11-15

    申请号：US13557725

    申请日：2012-07-25

    Applicant: Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

    Inventor： Andrew J. Beaumont-Smith ,  Honkai Tam ,  Daniel C. Murray ,  John H. Mylius ,  Peter J. Bannon ,  Pradeep Kanapathipillai

    IPC: G06F9/30

    CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

    Abstract translation: 在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。 其他依赖关系在第二个依赖关系数组中被跟踪。 第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。 第二个数组可能比第一个依赖数组慢得多。

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