公开(公告)号：US11921636B2

公开(公告)日：2024-03-05

申请号：US17972675

申请日：2022-10-25

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Joseph Zbiciak

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F15/80

CPC分类号： G06F12/0815 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30065 ,  G06F9/325 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026 ,  G06F2212/621

摘要： A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US20230315894A1

公开(公告)日：2023-10-05

申请号：US18146063

申请日：2022-12-23

申请人： DRFIRST.COM, INC.

发明人： Zilong Tang ,  James F. Chen ,  Chen Qian

IPC分类号： G06F21/62 ,  G06F21/60 ,  H04L9/08 ,  G06F16/248 ,  G06F12/0891 ,  G06F12/0862

CPC分类号： G06F21/6227 ,  G06F21/602 ,  H04L9/0869 ,  G06F21/6245 ,  G06F16/248 ,  G06F12/0891 ,  H04L9/0866 ,  G06F12/0862 ,  H04L9/088 ,  H04L9/0894 ,  G06F2212/45 ,  G06F2212/1052 ,  G06F2212/6026

摘要： Implementations provide self-consistent, temporary, secure storage of information. An example system includes short-term memory storing a plurality of key records and a cache storing a plurality of data records. The key records and data records are locatable using participant identifiers. Each key record includes a nonce and each data record includes an encrypted portion. The key records are deleted periodically. The system also includes memory storing instructions that cause the system to receive query parameters that include first participant identifiers and to obtain a first nonce. The first nonce is associated with the first participant identifiers in the short-term memory. The instructions also cause the system to obtain data records associated with the first participant identifiers in the cache, to build an encryption key using the nonce and the first participant identifiers, and to decrypt the encrypted portion of the obtained data records using the encryption key.

公开(公告)号：US11775439B2

公开(公告)日：2023-10-03

申请号：US17345855

申请日：2021-06-11

申请人： PAYPAL, INC.

发明人： Cheng Tian ,  Braden Christopher Ericson ,  Titus Woo

IPC分类号： G06F12/00 ,  G06F12/0862 ,  G06F16/957

CPC分类号： G06F12/0862 ,  G06F16/9574 ,  G06F2212/602 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028

摘要： A computer system monitors usage of an application on a computing device to identify one or more pre-fetch situations corresponding to a user of the computing device. The computer system determines whether the computing device is in a situation that corresponds to at least one of the identified one or more pre-fetch situations. In response to determining that the computing device is in the situation that corresponds to the at least one of the identified one or more pre-fetch situations, the computer system causes data corresponding to the application to be pre-fetched.

公开(公告)号：US20230153245A1

公开(公告)日：2023-05-18

申请号：US17865637

申请日：2022-07-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Insoon JO

IPC分类号： G06F12/0862

CPC分类号： G06F12/0862 ,  G06F2212/1024 ,  G06F2212/6026

摘要： A method of operating a disaggregated memory system includes receiving memory management requests from a host device, the memory management requests including context values having different values for plural workloads. The context values are transmitted to an accelerator memory including memory regions to set the context values for the memory regions based on the memory management requests. Prefetch target data is determined based on a context table and a memory access log, and prefetch information associated with the prefetch target data is transmitted to the accelerator memory. The context table includes the context values, and the memory access log is associated with the accelerator memory. The prefetch information is stored in a prefetch target buffer included in the accelerator memory.

公开(公告)号：US11645210B2

公开(公告)日：2023-05-09

申请号：US17652635

申请日：2022-02-25

申请人： Splunk Inc.

发明人： Ledion Bitincka ,  Alexandros Batsakis ,  Paul J. Lucas ,  Nicholas Robert Romito

IPC分类号： G06F12/00 ,  G06F12/0875 ,  G06F16/172 ,  G06F16/951 ,  G06F16/957 ,  G06F3/06 ,  G06F12/0802 ,  G06F16/14 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873

CPC分类号： G06F12/0875 ,  G06F3/061 ,  G06F3/0611 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F16/148 ,  G06F16/172 ,  G06F16/951 ,  G06F16/9574 ,  G06F2212/1021 ,  G06F2212/45 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028

摘要： Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.

公开(公告)号：US20190196971A1

公开(公告)日：2019-06-27

申请号：US16230120

申请日：2018-12-21

申请人： BULL SAS

发明人： Trong Ton PHAM ,  Lionel VINCENT ,  Grégoire PICHON

IPC分类号： G06F12/0862 ,  G06F16/172 ,  G06F16/182 ,  G06N20/00

CPC分类号： G06F12/0862 ,  G06F9/30047 ,  G06F16/172 ,  G06F16/182 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6026 ,  G06N20/00

摘要： A method for improving the execution time of a computer application comprises at least one cycle includes: a step of determining the type of memory access time sequence occurring during execution of the computer application; a step of preloading data, from a file system to a cache memory system, according to the determined type of memory access time sequence. The determination step is carried out by a learning model having been previously configured using a database of certain predetermined types of memory access time sequences.

公开(公告)号：US20190138312A1

公开(公告)日：2019-05-09

申请号：US16239766

申请日：2019-01-04

申请人： International Business Machines Corporation

发明人： RICHARD J. EICKEMEYER ,  SHELDON LEVENSTEIN ,  DAVID S. LEVITAN ,  MAURICIO J. SERRANO

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0862

CPC分类号： G06F9/3802 ,  G06F9/3891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/6026

摘要： Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

公开(公告)号：US20180232313A1

公开(公告)日：2018-08-16

申请号：US15882104

申请日：2018-01-29

申请人： ARM Limited

发明人： Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Jonas SVEDAS ,  Stephan DIESTELHORST

IPC分类号： G06F12/0871 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0808 ,  G06F12/0811 ,  G06F3/06

CPC分类号： G06F12/0871 ,  G06F3/064 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0895 ,  G06F2212/6026

摘要： A system cache and method of operating a system cache are provided. The system cache provides data caching in response to data access requests from plural system components. The system cache has data caching storage with plural entries, each entry storing a block of data items and each block of data items comprising plural sectors of data items, and each block of data items being stored in an entry of the data caching storage with an associated address portion. Sector use prediction circuitry is provided which has a set of pattern entries to store a set of sector use patterns. In response to a data access request received from a system component specifying one or more data items a selected pattern entry is selected in dependence on a system component identifier in the data access request and a sector use prediction is generated in dependence on a sector use pattern in the selected pattern entry. Further data items may then be retrieved which are not specified in the data access request but are indicated by the sector use prediction, and memory bandwidth usage is thereby improved.

公开(公告)号：US10037280B2

公开(公告)日：2018-07-31

申请号：US14726454

申请日：2015-05-29

申请人： QUALCOMM Incorporated

发明人： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab ,  Muhammad Umar Choudry

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/0862 ,  G06F12/109

CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

摘要： Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

公开(公告)号：US10013357B2

公开(公告)日：2018-07-03

申请号：US15269072

申请日：2016-09-19

申请人： Cavium, Inc.

发明人： Shubhendu Sekhar Mukherjee ,  David Albert Carlson ,  Srilatha Manne

IPC分类号： G06F12/00 ,  G06F12/0862 ,  G06F12/0897 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/6024 ,  G06F2212/6026

摘要： Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.