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公开(公告)号：US20180365012A1
公开(公告)日：2018-12-20
申请号：US16110917
申请日：2018-08-23
发明人： RICHARD J. EICKEMEYER , SHELDON B. LEVENSTEIN , DAVID S. LEVITAN , MAURICIO J. SERRANO , BRIAN W. THOMPTO
IPC分类号： G06F9/30 , G06F12/0897 , G06F12/0862 , G06F12/0875
CPC分类号： G06F9/30047 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1024 , G06F2212/452 , G06F2212/602 , G06F2212/6028 , H04L45/7457
摘要： A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an instruction cache. In response to the CLA subsequently hitting in the instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the instruction cache.
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公开(公告)号：US20170371658A1
公开(公告)日：2017-12-28
申请号：US15193338
申请日：2016-06-27
发明人： RICHARD J. EICKEMEYER , DAVID A. HRUSECKY , ELIZABETH A. MCGLONE , BRIAN W. THOMPTO , ALBERT J. VAN NORSTRAND, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3855 , G06F9/3824
摘要： Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.
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公开(公告)号：US20170329607A1
公开(公告)日：2017-11-16
申请号：US15155327
申请日：2016-05-16
IPC分类号： G06F9/30
摘要： Hazard avoidance in a multi-slice processor including adding, to a hazard table, an entry for an effective address, wherein the entry comprises an instruction tag (ITAG) offset for the effective address; fetching, by an instruction fetch unit, a processor instruction from a memory location using the effective address; determining that the hazard table includes the entry for the effective address; retrieving, from the hazard table, the ITAG offset for the effective address; identifying a prior internal operation (TOP) using the ITAG offset; and decoding the processor instruction into a load IOP with a dependency on the prior IOP.
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公开(公告)号：US20170315810A1
公开(公告)日：2017-11-02
申请号：US15141112
申请日：2016-04-28
IPC分类号： G06F9/30 , G06F12/0875
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/322 , G06F9/3806 , G06F12/0862 , G06F2212/6024
摘要： A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.
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公开(公告)号：US20190138312A1
公开(公告)日：2019-05-09
申请号：US16239766
申请日：2019-01-04
IPC分类号： G06F9/38 , G06F12/0875 , G06F12/0891 , G06F12/0862
CPC分类号： G06F9/3802 , G06F9/3891 , G06F12/0862 , G06F12/0875 , G06F12/0891 , G06F2212/452 , G06F2212/6026
摘要： Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.
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公开(公告)号：US20180260230A1
公开(公告)日：2018-09-13
申请号：US15980237
申请日：2018-05-15
发明人： RICHARD J. EICKEMEYER , DAVID A. HRUSECKY , ELIZABETH A. MCGLONE , BRIAN W. THOMPTO , ALBERT J. VAN NORSTRAND, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3824 , G06F9/3857
摘要： Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.
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公开(公告)号：US20170329715A1
公开(公告)日：2017-11-16
申请号：US15220028
申请日：2016-07-26
CPC分类号： G06F12/10 , G06F9/3802 , G06F9/3834 , G06F9/3838 , G06F9/384 , G06F9/3861 , G06F2212/251
摘要： Hazard avoidance in a multi-slice processor including adding, to a hazard table, an entry for an effective address, wherein the entry comprises an instruction tag (ITAG) offset for the effective address; fetching, by an instruction fetch unit, a processor instruction from a memory location using the effective address; determining that the hazard table includes the entry for the effective address; retrieving, from the hazard table, the ITAG offset for the effective address; identifying a prior internal operation (TOP) using the ITAG offset; and decoding the processor instruction into a load IOP with a dependency on the prior IOP.
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公开(公告)号：US20170269937A1
公开(公告)日：2017-09-21
申请号：US15072717
申请日：2016-03-17
CPC分类号： G06F9/3802 , G06F9/30043 , G06F9/32 , G06F9/3891 , G06F12/0862 , G06F12/0875 , G06F12/0891 , G06F2212/452 , G06F2212/6026
摘要： Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.
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公开(公告)号：US20170337132A1
公开(公告)日：2017-11-23
申请号：US15161418
申请日：2016-05-23
发明人： RICHARD J. EICKEMEYER , KIMBERLY M. FERNSLER , Guy L. GUTHRIE , DAVID A. HRUSECKY , ELIZABETH A. MCGLONE
IPC分类号： G06F12/0811 , G06F12/0875
CPC分类号： G06F12/0811 , G06F9/30138 , G06F12/0875 , G06F2212/283 , G06F2212/452
摘要： Accessing partial cachelines in a data cache including storing a first portion of a cacheline in a cache entry of the data cache; relaunching a load instruction targeting a second portion of the cacheline, wherein the second portion of the cacheline is not stored in the data cache; determining that the load instruction targets a portion of the cacheline not stored in the cache entry; storing the second portion of the cacheline in the data cache; and reading the second portion of the cacheline from the data cache according to the load instruction.
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公开(公告)号：US20170329608A1
公开(公告)日：2017-11-16
申请号：US15151609
申请日：2016-05-11
发明人： RICHARD J. EICKEMEYER , SHELDON B. LEVENSTEIN , DAVID S. LEVITAN , MAURICIO J. SERRANO, Jr. , BRIAN W. THOMPTO
IPC分类号： G06F9/30 , H04L12/743 , G06F12/0862 , G06F12/0875
CPC分类号： G06F9/30047 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1024 , G06F2212/452 , G06F2212/6028
摘要： A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an upper level instruction cache. In response to the CLA subsequently hitting in the upper level instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the upper level instruction cache.
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