- 专利标题: TECHNIQUES FOR DYNAMIC SEQUENTIAL INSTRUCTION PREFETCHING
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申请号: US15151609申请日: 2016-05-11
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公开(公告)号: US20170329608A1公开(公告)日: 2017-11-16
- 发明人: RICHARD J. EICKEMEYER , SHELDON B. LEVENSTEIN , DAVID S. LEVITAN , MAURICIO J. SERRANO, Jr. , BRIAN W. THOMPTO
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; H04L12/743 ; G06F12/0862 ; G06F12/0875
摘要:
A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an upper level instruction cache. In response to the CLA subsequently hitting in the upper level instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the upper level instruction cache.
公开/授权文献
- US10078514B2 Techniques for dynamic sequential instruction prefetching 公开/授权日:2018-09-18
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