-
公开(公告)号：US12112397B2
公开(公告)日：2024-10-08
申请号：US18334733
申请日：2023-06-14
申请人： Intel Corporation
发明人： Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Nadathur Rajagopalan Satish , Jeremy Bottleson , Farshad Akhbari , Altug Koker , Narayan Srinivasa , Dukhwan Kim , Sara S. Baghsorkhi , Justin E. Gottschlich , Feng Chen , Elmoustapha Ould-Ahmed-Vall , Kevin Nealis , Xiaoming Chen , Anbang Yao
IPC分类号： G06T1/20 , G06F9/30 , G06F9/38 , G06N3/04 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/08 , G06N3/084
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06N3/04 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/08 , G06N3/084
摘要： One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.
-
公开(公告)号：US12061464B2
公开(公告)日：2024-08-13
申请号：US17563424
申请日：2021-12-28
IPC分类号： G05B19/418 , G06F9/30 , G06F13/40 , H04L67/12 , G05B17/00
CPC分类号： G05B19/41885 , G05B19/4183 , G05B19/41835 , G05B19/41845 , G05B19/4185 , G05B19/41865 , G06F9/3017 , G06F13/4022 , H04L67/12 , G05B17/00 , G05B2219/13125 , G05B2219/13185 , G05B2219/2214 , G05B2219/31231 , G05B2219/32301 , G05B2219/32343 , G05B2219/32355 , G05B2219/32359 , G05B2219/32407 , G05B2219/40311
摘要： A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.
-
公开(公告)号：US11971817B2
公开(公告)日：2024-04-30
申请号：US17733258
申请日：2022-04-29
CPC分类号： G06F12/0253 , G06F9/3009 , G06F9/3017 , G06F12/0246
摘要： Techniques for managing lifecycles of sets of foreign resources are disclosed, including: opening, in a runtime environment configured to use a garbage collector to manage memory in a heap, a memory session; allocating a first subset of a set of foreign memory to a memory segment associated with the memory session, the foreign memory including off-heap memory that is not managed by the garbage collector; encountering, in the runtime environment, an instruction to close the memory session; responsive to encountering the instruction to close the memory session, deallocating the subset of the set of foreign memory.
-
公开(公告)号：US11960270B2
公开(公告)日：2024-04-16
申请号：US18085805
申请日：2022-12-21
IPC分类号： G05B19/418 , G06F9/30 , G06F13/40 , H04L67/12 , G05B17/00
CPC分类号： G05B19/41885 , G05B19/4183 , G05B19/41835 , G05B19/41845 , G05B19/4185 , G05B19/41865 , G06F9/3017 , G06F13/4022 , H04L67/12 , G05B17/00 , G05B2219/13125 , G05B2219/13185 , G05B2219/2214 , G05B2219/31231 , G05B2219/32301 , G05B2219/32343 , G05B2219/32355 , G05B2219/32359 , G05B2219/32407 , G05B2219/40311
摘要： A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.
-
公开(公告)号：US11861365B2
公开(公告)日：2024-01-02
申请号：US17306373
申请日：2021-05-03
申请人： SiFive, Inc.
发明人： Krste Asanovic , Andrew Waterman
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3844
摘要： Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
-
公开(公告)号：US11803381B2
公开(公告)日：2023-10-31
申请号：US17471167
申请日：2021-09-10
发明人： Weilin Wang , Yingbing Guan , Mengchen Yang
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/30047 , G06F9/30101 , G06F9/30174 , G06F9/30185 , G06F9/30189 , G06F9/3814 , G06F9/3857 , G06F9/455 , G06F9/45516 , G06F9/4812 , G06F11/0772
摘要： An instruction simulation device and a method thereof are provided. The simulation device includes a monitor, which is configured to determine whether a ready-for-execution instruction is an instruction under a new/extended instruction set sharing the same instruction set architecture as that of the processor. If the ready-for-execution instruction is an extended instruction, it is converted into a simulation program which consists of a compatible instruction sequence further composed of at least one native instruction of the processor or a compatible instruction recognizable/executable by the processor. An execution result of the extended instruction is simulated by executing the simulation program, thereby extending the service life of an electronic appliance embodied with the disclosed simulation device therein.
-
公开(公告)号：US11747797B2
公开(公告)日：2023-09-05
申请号：US17563413
申请日：2021-12-28
IPC分类号： G05B19/418 , G06F9/30 , G06F13/40 , H04L67/12 , G05B17/00
CPC分类号： G05B19/41885 , G05B19/4183 , G05B19/4185 , G05B19/41835 , G05B19/41845 , G05B19/41865 , G06F9/3017 , G06F13/4022 , H04L67/12 , G05B17/00 , G05B2219/13125 , G05B2219/13185 , G05B2219/2214 , G05B2219/31231 , G05B2219/32301 , G05B2219/32343 , G05B2219/32355 , G05B2219/32359 , G05B2219/32407 , G05B2219/40311
摘要： A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.
-
公开(公告)号：US11727527B2
公开(公告)日：2023-08-15
申请号：US17541413
申请日：2021-12-03
申请人： Intel Corporation
发明人： Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Nadathur Rajagopalan Satish , Jeremy Bottleson , Farshad Akhbari , Altug Koker , Narayan Srinivasa , Dukhwan Kim , Sara S. Baghsorkhi , Justin E. Gottschlich , Feng Chen , Elmoustapha Ould-Ahmed-Vall , Kevin Nealis , Xiaoming Chen , Anbang Yao
IPC分类号： G06T1/20 , G06N3/063 , G06F9/38 , G06F9/30 , G06N3/084 , G06N3/044 , G06N3/045 , G06N3/04 , G06N3/08
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06N3/04 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/08 , G06N3/084
摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.
-
公开(公告)号：US11709795B2
公开(公告)日：2023-07-25
申请号：US17525146
申请日：2021-11-12
发明人： Jaehoon Chung
CPC分类号： G06F15/8046 , G06F1/10 , G06F9/3017
摘要： Disclosed is an electronic device which includes a main processor, and a systolic array processor, and the systolic array processor includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements. The main processor translates source codes associated with the systolic array processor into commands of the systolic array processor, calculates a switching activity value based on the commands, and stores the translated commands and the switching activity value to a machine learning module, which is based on the systolic array processor.
-
公开(公告)号：US11704588B2
公开(公告)日：2023-07-18
申请号：US16144963
申请日：2018-09-27
申请人： Intel Corporation
发明人： Xiang Zou , Justin Hogaboam
CPC分类号： G06N10/70 , G06F9/22 , G06F9/3017 , G06F9/30101 , G06F9/3877
摘要： Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.
-
-
-
-
-
-
-
-
-
搜索结果
1510 条记录 (耗时 0.025 秒)
