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    Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders
    1.
    发明授权
    Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders 有权

    公开(公告)号：US12093694B2

    公开(公告)日：2024-09-17

    申请号：US17214693

    申请日：2021-03-26

    申请人： Intel Corporation

    发明人： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3804 ,  G06F9/3856

    摘要： Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.

    RETURN ADDRESS STACK WITH BRANCH MISPREDICT RECOVERY
    2.
    发明公开
    RETURN ADDRESS STACK WITH BRANCH MISPREDICT RECOVERY 审中-公开

    公开(公告)号：US20240220267A1

    公开(公告)日：2024-07-04

    申请号：US18399959

    申请日：2023-12-29

    申请人： Akeana, Inc.

    发明人： James Youngsae Cho ,  Rabin Sugumar

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

    DYNAMIC BRANCH CAPABLE MICRO-OPERATIONS CACHE
    4.
    发明公开
    DYNAMIC BRANCH CAPABLE MICRO-OPERATIONS CACHE 审中-公开

    公开(公告)号：US20240118896A1

    公开(公告)日：2024-04-11

    申请号：US17960583

    申请日：2022-10-05

    申请人： Nokia Solutions and Networks Oy

    发明人： Pranjal Kumar Dutta

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30047 ,  G06F9/30058

    摘要： Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support increased efficiency in utilization of a micro-operations cache (UC) of a processor. Various example embodiments for supporting increased efficiency in utilization of a UC of a processor may be configured to support increased efficiency in utilization of the UC of the processor based on configuration of the processor such that UC lines created by a prediction window (PW) during execution of a set of instructions by the processor are not invalidated on misprediction of a branch instruction in the set of instructions.

    Control flow prediction
    6.
    发明授权
    Control flow prediction 有权

    公开(公告)号：US11915004B2

    公开(公告)日：2024-02-27

    申请号：US17556166

    申请日：2021-12-20

    申请人： Arm Limited

    发明人： Houdhaifa Bouzguarrou ,  Thibaut Elie Lanois ,  Guillaume Bolbenes

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/30054 ,  G06F9/3816

    摘要： A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

    Securing Conditional Speculative Instruction Execution
    7.
    发明公开
    Securing Conditional Speculative Instruction Execution 审中-公开

    公开(公告)号：US20240020128A1

    公开(公告)日：2024-01-18

    申请号：US18353558

    申请日：2023-07-17

    申请人： Lodestar Licensing Group LLC

    发明人： Steven Jeffrey Wallach

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30058

    摘要： A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

    Apparatus and method for speculative execution information flow tracking
    8.
    发明授权
    Apparatus and method for speculative execution information flow tracking 有权

    公开(公告)号：US11797309B2

    公开(公告)日：2023-10-24

    申请号：US16728722

    申请日：2019-12-27

    申请人： Intel Corporation

    发明人： Carlos Rozas ,  Francis McKeen ,  Pasquale Cocchini ,  Meltem Ozsoy ,  Matthew Fernandez

    IPC分类号： G06F9/38 ,  G06F9/50 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/5011

    摘要： An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities. For example, one embodiment of a processor comprises: an instruction fetcher to fetch instructions from a cache or system memory; a branch predictor to speculate a first instruction path to be taken comprising a first sequence of instructions; a decoder to decode the first sequence of instructions; execution circuitry to execute the first sequence of instructions and process data associated with the instruction to generate results; information flow tracking circuitry and/or logic to: assign labels to all or a plurality of instructions in the first sequence of instructions, track resource usage of the plurality of instructions using the labels, merge sets of labels to remove redundancies; and responsive to detecting that the first instruction path was mis-predicted, generating one or more summaries comprising resources affected by one or more of the first sequence of instructions; and recycling labels responsive to retirement of instructions associated with the labels.