公开(公告)号：US20230409335A1

公开(公告)日：2023-12-21

申请号：US17843179

申请日：2022-06-17

申请人： Intel Corporation

发明人： Mathew Lowes ,  Jared Warner Stark, IV ,  Martin Licht

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3844 ,  G06F9/321 ,  G06F9/3806

摘要： Techniques for selective disable of history-based predictors on mode transitions are described. An example apparatus comprises first circuitry to provide a history-based prediction, and second circuitry coupled to the first circuitry to selectively block and unblock a prediction from the first circuitry after a mode transition. Other examples are disclosed and claimed.

公开(公告)号：US12093694B2

公开(公告)日：2024-09-17

申请号：US17214693

申请日：2021-03-26

申请人： Intel Corporation

发明人： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3804 ,  G06F9/3856

摘要： Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.

公开(公告)号：US08904112B2

公开(公告)日：2014-12-02

申请号：US13843885

申请日：2013-03-15

申请人： Intel Corporation

发明人： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC分类号： G06F12/00 ,  G06F1/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

摘要： A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

摘要翻译： 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US20230185572A1

公开(公告)日：2023-06-15

申请号：US17549192

申请日：2021-12-13

申请人： Intel Corporation

发明人： Martin Licht ,  Jonathan Combs

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/3802 ,  G06F9/3818

摘要： An embodiment of an integrated circuit may comprise a core and an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, where the instruction decoder includes two or more decode clusters in a parallel arrangement, and circuitry to offline a decode cluster of the two or more decode clusters. Other embodiments are disclosed and claimed.

公开(公告)号：US20150089143A1

公开(公告)日：2015-03-26

申请号：US14557474

申请日：2014-12-02

申请人： Intel Corporation

发明人： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

摘要： A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

摘要翻译： 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US20230401067A1

公开(公告)日：2023-12-14

申请号：US17840029

申请日：2022-06-14

申请人： Intel Corporation

发明人： Mathew Lowes ,  Martin Licht ,  Jonathan Combs

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/3016

摘要： In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region. Other embodiments are described and claimed.

公开(公告)号：US20220405102A1

公开(公告)日：2022-12-22

申请号：US17352671

申请日：2021-06-21

申请人： Intel Corporation

发明人： Mathew Lowes ,  Martin Licht

IPC分类号： G06F9/38 ,  G06F9/32 ,  G06F9/30

摘要： An embodiment of an integrated circuit may comprise a return stack buffer (RSB), a speculative return stack buffer (SRSB), and circuitry coupled to the RSB and the SRSB, the circuitry to track a count until the SRSB is empty at a time of a prediction by a branch prediction unit, and return an output from the branch prediction unit that corresponds to one of the RSB and the SRSB based at least in part on the count until the SRSB is empty. Other embodiments are disclosed and claimed.

公开(公告)号：US20220318020A1

公开(公告)日：2022-10-06

申请号：US17214693

申请日：2021-03-26

申请人： Intel Corporation

发明人： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

IPC分类号： G06F9/38

摘要： Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.

公开(公告)号：US09098284B2

公开(公告)日：2015-08-04

申请号：US14557474

申请日：2014-12-02

申请人： Intel Corporation

发明人： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC分类号： G06F12/00 ,  G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

摘要： A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

摘要翻译： 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。