知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

157 records (took 0.021 seconds)

    Exit history based branch prediction
    1.
    发明授权
    Exit history based branch prediction 有权

    公开(公告)号：US12197917B2

    公开(公告)日：2025-01-14

    申请号：US17849994

    申请日：2022-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, Jr. ,  Paul D. Gauvreau

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory. The fetch-packet contains a bitwise distance from an entry point of the first hyper-block to a predicted exit point. A first branch instruction of the first hyper-block is executed that corresponds to a first exit point. The first branch instruction includes an address corresponding to an entry point of a second hyper-block. Responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point is stored. A program counter is moved from the first exit point of the first hyper-block to the entry point of the second hyper-block.

    Memory pipeline control in a hierarchical memory system
    2.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US12197332B2

    公开(公告)日：2025-01-14

    申请号：US18584181

    申请日：2024-02-22

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Nested loop control
    4.
    发明授权
    Nested loop control 有权

    公开(公告)号：US12175244B2

    公开(公告)日：2024-12-24

    申请号：US18507222

    申请日：2023-11-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F9/30

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

    Nested loop control
    7.
    发明授权
    Nested loop control 有权

    公开(公告)号：US11816485B2

    公开(公告)日：2023-11-14

    申请号：US17367384

    申请日：2021-07-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F9/30

    CPC classification number: G06F9/30065 ,  G06F9/3013

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Patent Agency Ranking