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公开(公告)号：US12086074B2
公开(公告)日：2024-09-10
申请号：US18321050
申请日：2023-05-22
IPC分类号： G06F12/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F12/1045 , G06F17/16 , H03H17/06 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US20240211254A1
公开(公告)日：2024-06-27
申请号：US18594461
申请日：2024-03-04
发明人： Timothy David Anderson , Duc Quang Bui , Mujibur Rahman , Joseph Raymond Michael Zbiciak , Eric Biscondi , Peter Dent , Jelena Milanovic , Ashish Shrivastava
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30112 , G06F9/3893
摘要： A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
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公开(公告)号：US11922166B2
公开(公告)日：2024-03-05
申请号：US18097552
申请日：2023-01-17
发明人： Timothy David Anderson , Duc Quang Bui , Mujibur Rahman , Joseph Raymond Michael Zbiciak , Eric Biscondi , Peter Dent , Jelena Milanovic , Ashish Shrivastava
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30112 , G06F9/3893
摘要： A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
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公开(公告)号：US20230289296A1
公开(公告)日：2023-09-14
申请号：US18321050
申请日：2023-05-22
IPC分类号： G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
CPC分类号： G06F12/1045 , G06F9/30145 , G06F9/345 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F9/30065 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30149 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/48 , G06F17/16 , G06F9/30032 , G06F9/30072 , G06F9/3887 , H03H17/0664 , G06F9/30098 , G06F9/3016 , G06F9/32 , G06F9/3802 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F11/10 , G06F9/3822 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F15/7807
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US11755322B2
公开(公告)日：2023-09-12
申请号：US16580490
申请日：2019-09-24
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30043
摘要： Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.
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公开(公告)号：US11604652B2
公开(公告)日：2023-03-14
申请号：US17164448
申请日：2021-02-01
IPC分类号： G06F7/76 , G06F9/30 , G06F12/0811
摘要： A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.
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公开(公告)号：US11556338B2
公开(公告)日：2023-01-17
申请号：US16852690
申请日：2020-04-20
发明人： Timothy David Anderson , Duc Quang Bui , Mujibur Rahman , Joseph Raymond Michael Zbiciak , Eric Biscondi , Peter Dent , Jelena Milanovic , Ashish Shrivastava
摘要： A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
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公开(公告)号：US11550573B2
公开(公告)日：2023-01-10
申请号：US17126156
申请日：2020-12-18
IPC分类号： G06F1/3287 , G06F9/30 , G06F1/3206 , G06F9/38
摘要： In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.
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公开(公告)号：US20210357219A1
公开(公告)日：2021-11-18
申请号：US17391143
申请日：2021-08-02
IPC分类号： G06F9/30
摘要： The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.
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公开(公告)号：US20200091943A1
公开(公告)日：2020-03-19
申请号：US16694205
申请日：2019-11-25
摘要： A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.
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