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公开(公告)号：US11237831B2
公开(公告)日：2022-02-01
申请号：US16878611
申请日：2020-05-20
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US12086074B2
公开(公告)日：2024-09-10
申请号：US18321050
申请日：2023-05-22
IPC分类号： G06F12/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F12/1045 , G06F17/16 , H03H17/06 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US20230289296A1
公开(公告)日：2023-09-14
申请号：US18321050
申请日：2023-05-22
IPC分类号： G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
CPC分类号： G06F12/1045 , G06F9/30145 , G06F9/345 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F9/30065 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30149 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/48 , G06F17/16 , G06F9/30032 , G06F9/30072 , G06F9/3887 , H03H17/0664 , G06F9/30098 , G06F9/3016 , G06F9/32 , G06F9/3802 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F11/10 , G06F9/3822 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F15/7807
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US11604652B2
公开(公告)日：2023-03-14
申请号：US17164448
申请日：2021-02-01
IPC分类号： G06F7/76 , G06F9/30 , G06F12/0811
摘要： A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.
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公开(公告)号：US12099843B2
公开(公告)日：2024-09-24
申请号：US18120601
申请日：2023-03-13
IPC分类号： G06F9/30 , G06F12/0811
CPC分类号： G06F9/3016 , G06F9/30065 , G06F9/30098 , G06F12/0811
摘要： A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.
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公开(公告)号：US20240211411A1
公开(公告)日：2024-06-27
申请号：US18587416
申请日：2024-02-26
IPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
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公开(公告)号：US11921643B2
公开(公告)日：2024-03-05
申请号：US17690344
申请日：2022-03-09
IPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/06 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
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公开(公告)号：US11669463B2
公开(公告)日：2023-06-06
申请号：US17588416
申请日：2022-01-31
IPC分类号： G06F12/10 , G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/781 , G06F15/7807 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US11307791B2
公开(公告)日：2022-04-19
申请号：US16422522
申请日：2019-05-24
摘要： A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.
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公开(公告)号：US11301248B2
公开(公告)日：2022-04-12
申请号：US16878603
申请日：2020-05-20
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
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