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12 条记录 (耗时 0.022 秒)

    Slot/sub-slot prefetch architecture for multiple memory requestors
    1.
    发明授权
    Slot/sub-slot prefetch architecture for multiple memory requestors 有权

    公开(公告)号：US10394718B2

    公开(公告)日：2019-08-27

    申请号：US15899138

    申请日：2018-02-19

    申请人： Texas Instruments Incorporated

    发明人： Kai Chirca ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson

    IPC分类号： G06F12/00 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F9/38

    摘要： A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

    Secure Master and Secure Guest Endpoint Security Firewall
    2.
    发明申请
    Secure Master and Secure Guest Endpoint Security Firewall 审中-公开
    安全主控和安全访客端点安全防火墙

    公开(公告)号：US20140143849A1

    公开(公告)日：2014-05-22

    申请号：US14062002

    申请日：2013-10-24

    申请人： Texas Instruments Incorporated

    发明人： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

    IPC分类号： H04L29/06

    CPC分类号： G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

    摘要翻译： 本发明是具有安全层级的安全防火墙，包括：安全主机（SM）; 安全客人（SG）; 和非安全（NS）。 有一个安全的主人和n个安全的客人。 防火墙包括一个用于安全主控的安全区域和一个用于安全访客的安全区域。 SM区域仅允许从安全主机访问，并且SG区域允许来自任何安全事务的访问。 最后，非安全区域可以实现两种方式。 在第一个选项中，只有在非安全事务时才可以访问非安全区域。 在第二个选项中，非安全区域可以被访问任何处理核心。 在第二个选项中，如果安全身份是安全主机或安全访客，则访问权限降级到非安全访问。 如果不需要两个安全级别，则安全主机可以解锁SM区域，以允许任何安全访客访问SM区域。

    Slot/sub-slot prefetch architecture for multiple memory requestors
    3.
    发明授权
    Slot/sub-slot prefetch architecture for multiple memory requestors 有权

    公开(公告)号：US11074190B2

    公开(公告)日：2021-07-27

    申请号：US16552418

    申请日：2019-08-27

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Kai Chirca ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson

    IPC分类号： G06F12/00 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F9/38

    摘要： A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

    Distributed power control for controlling power consumption based on detected activity of logic blocks
    9.
    再颁专利
    Distributed power control for controlling power consumption based on detected activity of logic blocks 有权
    分布式功率控制，用于根据检测到的逻辑块的活动来控制功耗

    公开(公告)号：USRE46193E1

    公开(公告)日：2016-11-01

    申请号：US14303262

    申请日：2014-06-12

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

    IPC分类号： G06F1/32

    摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

    摘要翻译： 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。