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公开(公告)号：US10019375B2
公开(公告)日：2018-07-10
申请号：US15269930
申请日：2016-09-19
发明人： Hiroyuki Usui , Seiji Maeda
IPC分类号： G06F12/0895 , G06F12/0864 , G06F12/084 , G06F12/0811 , G06F12/0842 , G06F12/0886 , G06F12/121
CPC分类号： G06F12/0895 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0864 , G06F12/0886 , G06F12/121 , G06F2212/1016 , G06F2212/1024 , G06F2212/1028 , G06F2212/401 , G06F2212/6042 , Y02D10/13
摘要： A cache device has a data memory capable of storing a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form, and a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including uncompressed data writing state information, an absence flag, and a compression information field. In case of modifying only part of a cache line, i.e., a partial write, a request converter converts a write request into a read request, and a read-out piece of data is decompressed and written in a write status buffer. Data may be written from the write status buffer to the data memory without being compressed, which eliminates a need for decompression and compression for every writing or modifying operation of a piece of partial data, thereby reducing latency and power consumption.
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公开(公告)号：US20170293561A1
公开(公告)日：2017-10-12
申请号：US15270331
申请日：2016-09-20
IPC分类号： G06F12/0862 , G06F13/16 , G06F12/0891 , G06F12/0811 , G06F12/084
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/084 , G06F12/0886 , G06F12/0891 , G06F12/0897 , G06F13/1668 , G06F2212/1021 , G06F2212/602 , G06F2212/6024 , G06F2212/62
摘要： Systems and methods for managing memory access bandwidth include a spatial locality predictor. The spatial locality predictor includes a memory region table with prediction counters associated with memory regions of a memory. When cache lines are evicted from a cache, the sizes of the cache lines which were accessed by a processor are used for updating the prediction counters. Depending on values of the prediction counters, the sizes of cache lines which are likely to be used the processor predicted for the corresponding memory regions. Correspondingly, the memory access bandwidth between the processor and the memory may be reduced to fetch a smaller size data than a full cache line if the size of the cache line likely to be used is predicted to be less than that of the full cache line.
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公开(公告)号：US09684604B2
公开(公告)日：2017-06-20
申请号：US14792869
申请日：2015-07-07
发明人： Seungjin Yang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0895 , G06F12/0886
CPC分类号： G06F12/0895 , G06F12/0886 , G06F2212/401 , G06F2212/608
摘要： An electronic device with a cache memory and a method of operating the electronic device are provided. The electronic device includes a cache memory including a plurality of cache lines each of which includes a first area with at least one storage space and a second area with at least one storage space, where the at least one storage space of the first area has a first size and the at least one storage space of the second area has a second size different from the first size, and a cache controller for storing the data requested for storage in one of the storage spaces of the first or second area, according to a compression factor associated with the data requested for storage when a request is made to store data in the cache memory.
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公开(公告)号：US09582426B2
公开(公告)日：2017-02-28
申请号：US13970817
申请日：2013-08-20
CPC分类号： G06F12/0871 , G06F12/0886 , G06F12/12 , G06F2212/401 , G06F2212/6042 , G06F2212/69
摘要： A computing element, system, and method for implementing control structures for a compressed cache in hardware. Embodiments provide a first engine configured to allocate and deallocate virtual memory pages and physical memory pages from pools of available pages to store received data to the compressed cache, a second engine configured to compress received data and store the compressed data. Embodiments also provide for embedding data within the virtual and physical memory pages to indicate page size, type, and data compression.
摘要翻译： 用于在硬件中实现压缩缓存的控制结构的计算元件，系统和方法。 实施例提供了第一引擎，其被配置为从可用页面池中分配和释放虚拟存储器页面和物理存储器页面以将接收的数据存储到压缩高速缓存，第二引擎被配置为压缩接收到的数据并存储压缩数据。 实施例还提供在虚拟和物理存储器页面内嵌入数据以指示页面大小，类型和数据压缩。
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5.发明授权Method and apparatus for a partial-address select-signal generator with address shift 有权具有地址偏移的部分地址选择信号发生器的方法和装置公开(公告)号：US09411724B2
公开(公告)日：2016-08-09
申请号：US13993062
申请日：2011-12-21
申请人： Lutz Naethke , Eric Desmarais , Ralf Goettsche
发明人： Lutz Naethke , Eric Desmarais , Ralf Goettsche
CPC分类号： G06F12/0615 , G06F1/3237 , G06F1/3296 , G06F9/30043 , G06F9/345 , G06F9/3895 , G06F12/04 , G06F12/0886 , G06F2212/1028 , Y02D10/128 , Y02D10/13 , Y02D10/172
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift. For example, in one embodiment, such means may include receiving a plurality of address lines; splitting the plurality of address lines into a first sub-set of the plurality of address lines and a remaining sub-set of the plurality of address lines; passing the first subset of the plurality of address lines to an upper processing path; passing the remaining sub-set of the plurality of address lines to a lower processing path in parallel with the upper processing path; generating intermediate code on the upper processing path from the first sub-set of the plurality of address lines and from an intermediate carry result from the remaining sub-set of the plurality of address lines on the lower processing path; passing a hot signal type to a decoding unit on the upper processing path, wherein the hot signal type designates a decode scheme; generating specific hot-signal select line code based on the intermediate code and the hot signal type; and adopting decode scheme of the hot-signal select lines according to information from the lower processing path. Structure for performing the same are further disclosed.
摘要翻译： 根据本文公开的实施例，提供了用于实现和使用具有地址移位的部分地址选择信号发生器的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括接收多个地址线; 将多个地址线分割成多个地址线的第一子集和多个地址线的剩余子集; 将多个地址线的第一子集传送到上层处理路径; 将多个地址线的剩余子集合与上处理路径并行地传送到下处理路径; 从所述多个地址线的所述第一子集和所述下处理路径上的所述多个地址线的剩余子集的中间进位结果生成所述上处理路径上的中间码; 将热信号类型传送到上位处理路径上的解码单元，其中热信号类型指定解码方案; 基于中间码和热信号类型产生特定的热信号选择线路码; 并根据来自较低处理路径的信息采用热信号选择线的解码方案。 进一步公开了其结构。
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公开(公告)号：US09367412B2
公开(公告)日：2016-06-14
申请号：US13532312
申请日：2012-06-25
CPC分类号： G06F11/2092 , G06F12/0886 , G06F12/0888
摘要： A network-based storage system includes multiple storage devices and system controllers. Each storage device in multiple aggregates of storage devices can include ownership portion(s) that are configured to indicate a system controller to which it belongs. First and second system controllers can form an HA pair, and can be in communication with each other, the storage devices, and a separate host server. A first system controller controls an aggregate of storage devices and can facilitate an automated hotswap replacement of a second system controller that controls another aggregate of storage devices with a separate third system controller that subsequently controls the other aggregate of storage devices. The first system controller can take over control of the second aggregate of storage devices during the automated hotswap replacement of the second system controller, and can exchange system identifiers and ownership portion information with the separate third system controller automatically during the hotswap.
摘要翻译： 基于网络的存储系统包括多个存储设备和系统控制器。 存储设备的多个聚合中的每个存储设备可以包括被配置为指示其所属的系统控制器的所有权部分。 第一和第二系统控制器可以形成HA对，并且可以彼此通信，存储设备和单独的主机服务器。 第一系统控制器控制存储设备的聚合，并且可以促进第二系统控制器的自动换热替换，所述第二系统控制器利用随后控制另一个存储设备的集合的单独的第三系统控制器来控制另一个存储设备的集合。 在第二系统控制器的自动换热更换期间，第一系统控制器可以接管对第二组存储设备的控制，并且可以在热置换期间自动地与单独的第三系统控制器交换系统标识符和所有权部分信息。
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7.发明申请公开(公告)号：US20160139927A1
公开(公告)日：2016-05-19
申请号：US14734862
申请日：2015-06-09
CPC分类号： G06F12/0875 , G06F9/30101 , G06F9/382 , G06F9/3853 , G06F12/0886 , G06F2212/452
摘要： A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.
摘要翻译： 一种用于处理指令的技术包括检查处理器的指令流中的指令以确定指令的属性。 属性指示指令是否可能属于经过解码 - 时间指令优化（DTIO）的指令序列。 确定多个指令的属性是否兼容包含在同一组的指令序列中。 具有兼容属性的指令被分组为第一指令组。 第一指令组的指令在形成第一指令组之后被解码。 基于解码来验证第一指令组是否实际包括DTIO序列。 基于验证，根据第一指令组的指令执行DTIO，或者不对第一指令组的指令执行DTIO。
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8.发明申请公开(公告)号：US20160139925A1
公开(公告)日：2016-05-19
申请号：US14543434
申请日：2014-11-17
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/30101 , G06F9/382 , G06F9/3853 , G06F12/0886 , G06F2212/452
摘要： A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.
摘要翻译： 一种用于处理指令的技术包括检查处理器的指令流中的指令以确定指令的属性。 属性指示指令是否可能属于经过解码 - 时间指令优化（DTIO）的指令序列。 确定多个指令的属性是否兼容包含在同一组的指令序列中。 具有兼容属性的指令被分组为第一指令组。 第一指令组的指令在形成第一指令组之后被解码。 基于解码来验证第一指令组是否实际包括DTIO序列。 基于验证，根据第一指令组的指令执行DTIO，或者不对第一指令组的指令执行DTIO。
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9.发明授权Electronic circuit for fitting a virtual address range to a physical memory containing faulty address 有权用于将虚拟地址范围拟合到包含故障地址的物理存储器的电子电路公开(公告)号：US09343185B2
公开(公告)日：2016-05-17
申请号：US14037487
申请日：2013-09-26
IPC分类号： G06F12/00 , G11C29/00 , G06F9/445 , G06F9/32 , G06F12/08 , G06F11/10 , G06F12/12 , G06F12/06 , G06F13/22 , G06F13/38 , G06F12/10 , G06F12/04 , G11C15/00 , G11C8/06
CPC分类号： G11C29/76 , G06F8/65 , G06F9/328 , G06F11/1008 , G06F12/04 , G06F12/0638 , G06F12/0868 , G06F12/0886 , G06F12/1027 , G06F12/109 , G06F12/126 , G06F13/225 , G06F13/385 , G11C8/06 , G11C15/00
摘要： A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
摘要翻译： 具有可变大小的故障存储器地址块的存储器连接到存储器中存储地址范围的数据值的TCAM。 地址范围对应于与偏移相结合的虚拟地址，远离失败的存储器地址。 连接到TCAM的还原电路基于虚拟地址产生每个编程的地址范围的输出。 连接到还原电路的优先编码器从缩小电路中选择第一范围，并将第一范围传递给随机存取存储器（RAM）。 响应虚拟地址将地址置于地址范围之一中，优先级编码器将包含虚拟地址的第一范围传递给RAM，RAM根据第一范围将相应的偏移值传递给加法器。 Adder计算一个物理内存地址，将虚拟地址指向功能内存位置。
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公开(公告)号：US09342459B2
公开(公告)日：2016-05-17
申请号：US10635870
申请日：2003-08-05
CPC分类号： G06F12/0886 , G06F8/4434 , G06F12/121 , G06F2212/401
摘要： A user visiting a space is equipped with a mobile device in communication with a service system. Media items held by the service system are associated with various locations around the space and a user arriving at such a location is presented with the corresponding item or items. Preferably, these media items are pre-emptively loaded into a cache of the user's mobile device in dependence on the user's progress around the space. Items can also be flushed from cache on this basis. Instead of, or as a precursor to, flushing an item from cache to free up space, the cache space occupied by an item is reduced by degrading it.
摘要翻译： 访问空间的用户配备有与服务系统通信的移动设备。 由服务系统保持的媒体项目与空间周围的各种位置相关联，并且到达该位置的用户被呈现相应的项目。 优选地，这些媒体项目根据用户在空间周围的进展而被先占地加载到用户的移动设备的高速缓存中。 在这个基础上也可以从缓存中刷新项目。 或者作为从缓存中冲洗物品以释放空间的前兆，而不是通过降级来减少物品占用的高速缓存空间。
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