知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.015 seconds)

    COST-AWARE CACHE REPLACEMENT
    1.
    发明申请
    COST-AWARE CACHE REPLACEMENT 审中-公开

    公开(公告)号：US20190018798A1

    公开(公告)日：2019-01-17

    申请号：US16134933

    申请日：2018-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Rami Mohammad AL SHEIKH ,  Shivam PRIYADARSHI ,  Harold Wade CAIN III

    IPC: G06F12/123 ,  G06F12/128 ,  G06F12/127

    Abstract: Systems and methods relate to cost-aware cache management policies. In a cost-aware least recently used (LRU) replacement policy, temporal locality as well as miss cost is taken into account in selecting a cache line for replacement, wherein the miss cost is based on an associated operation type including instruction cache read, data cache read, data cache write, prefetch, and write back. In a cost-aware dynamic re-reference interval prediction (DRRIP) based cache management policy, miss costs associated with operation types pertaining to a cache line are considered for assigning re-reference interval prediction values (RRPV) for inserting the cache line, pursuant to a cache miss and for updating the RRPV upon a hit for the cache line. The operation types comprise instruction cache access, data cache access, prefetch, and write back. These policies improve victim selection, while minimizing cache thrashing and scans.

    COST-AWARE CACHE REPLACEMENT
    4.
    发明申请
    COST-AWARE CACHE REPLACEMENT 审中-公开

    公开(公告)号：US20170293571A1

    公开(公告)日：2017-10-12

    申请号：US15271167

    申请日：2016-09-20

    Applicant: QUALCOMM Incorporated

    Inventor： Rami Mohammad A. AL SHEIKH ,  Shivam PRIYADARSHI ,  Harold Wade CAIN, III

    IPC: G06F12/123 ,  G06F12/127

    CPC classification number: G06F12/124 ,  G06F12/123 ,  G06F12/127 ,  G06F12/128

    Abstract: Systems and methods relate to cost-aware cache management policies. In a cost-aware least recently used (LRU) replacement policy, temporal locality as well as miss cost is taken into account in selecting a cache line for replacement, wherein the miss cost is based on an associated operation type including instruction cache read, data cache read, data cache write, prefetch, and write back. In a cost-aware dynamic re-reference interval prediction (DRRIP) based cache management policy, miss costs associated with operation types pertaining to a cache line are considered for assigning re-reference interval prediction values (RRPV) for inserting the cache line, pursuant to a cache miss and for updating the RRPV upon a hit for the cache line. The operation types comprise instruction cache access, data cache access, prefetch, and write back. These policies improve victim selection, while minimizing cache thrashing and scans.

    HIERARCHICAL REGISTER FILE SYSTEM
    5.
    发明申请
    HIERARCHICAL REGISTER FILE SYSTEM 审中-公开
    分层寄存器文件系统

    公开(公告)号：US20170060593A1

    公开(公告)日：2017-03-02

    申请号：US14843921

    申请日：2015-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Anil KRISHNA ,  Rodney Wayne SMITH ,  Sandeep Suresh NAVADA ,  Shivam PRIYADARSHI ,  Niket Kumar CHOUDHARY ,  Raguram DAMODARAN

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30105 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/3867

    Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.

    Abstract translation: 系统和方法涉及包括1级物理寄存器文件（L1 PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。 识别在处理器的指令流水线中执行的指令的生成的子集，其具有用于一个或多个未来指令的高似然性。 生产的子集存储在L1 PRF中，而所有生产都存储在后备PRF中。

    SELECTIVE REFRESH MECHANISM FOR DRAM
    6.
    发明申请
    SELECTIVE REFRESH MECHANISM FOR DRAM 审中-公开

    公开(公告)号：US20190013062A1

    公开(公告)日：2019-01-10

    申请号：US15644737

    申请日：2017-07-07

    Applicant: QUALCOMM Incorporated

    Inventor： Francois Ibrahim ATALLAH ,  Gregory Michael WRIGHT ,  Shivam PRIYADARSHI ,  Garrett Michael DRAPALA ,  Harold Wade CAIN, III ,  Erik HEDBERG

    IPC: G11C11/406 ,  G06F12/128 ,  G06F12/122 ,  G06F12/0871

    Abstract: Systems and methods for selective refresh of a cache, such as a last-level cache implemented as an embedded DRAM (eDRAM). A refresh bit and a reuse bit are associated with each way of at least one set of the cache. A least recently used (LRU) stack tracks positions of the ways, with positions towards a most recently used position of a threshold comprising more recently used positions and positions towards a least recently used position of the threshold comprise less recently used positions. A line in a way is selectively refreshed if the position of the way is one of the more recently used positions and if the refresh bit associated with the way is set, or the position of the way is one of the less recently used positions and if the refresh bit and the reuse bit associated with the way are both set.

    METHOD, APPARATUS, AND SYSTEM FOR REDUCING LIVE READINESS CALCULATIONS IN RESERVATION STATIONS
    7.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR REDUCING LIVE READINESS CALCULATIONS IN RESERVATION STATIONS 审中-公开

    公开(公告)号：US20190332385A1

    公开(公告)日：2019-10-31

    申请号：US15963126

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Rodney Wayne SMITH ,  Raghavan MADHAVAN ,  Luke YEN ,  Shivam PRIYADARSHI ,  Yusuf Cagatay TEKMEN

    IPC: G06F9/38

    Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

Patent Agency Ranking