公开(公告)号：US12099451B2

公开(公告)日：2024-09-24

申请号：US17489726

申请日：2021-09-29

申请人： Advanced Micro Devices, Inc.

发明人： Paul J. Moyer

IPC分类号： G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/127

CPC分类号： G06F12/122 ,  G06F12/123 ,  G06F12/124 ,  G06F12/127 ,  G06F2212/60

摘要： Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a binary tree that tracks recency of data blocks in the cache.

公开(公告)号：US11940930B2

公开(公告)日：2024-03-26

申请号：US17875572

申请日：2022-07-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC分类号： G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

公开(公告)号：US10387045B2

公开(公告)日：2019-08-20

申请号：US14902748

申请日：2014-07-03

申请人： AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

发明人： Tae Sun Chung ,  Rize Jin ,  Hyung Ju Cho

IPC分类号： G06F3/06 ,  G06F12/12 ,  G06F12/08 ,  G11C16/06 ,  G06F12/123 ,  G11C16/34 ,  G06F12/127 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0868

摘要： The present invention relates to an apparatus and a method for managing a buffer having three states on the basis of a flash memory and, more specifically, to an apparatus and a method for improving the performance of a database management system (DBMS) on the basis of the flash memory and a use life span of a storage device by reducing a writing operation for a flash memory device in which the writing operation is very slow in comparison with a reading operation, through an efficient buffer managing method and a new index node split policy. To this end, the buffer management device having three states on the basis of the flash memory according to an embodiment of the present invention comprises: a buffer memory unit; a list management unit; a buffer memory management unit; and a log buffer unit.

公开(公告)号：US20190057034A1

公开(公告)日：2019-02-21

申请号：US15679961

申请日：2017-08-17

申请人： YEN HSIANG CHEW

发明人： YEN HSIANG CHEW

IPC分类号： G06F12/0842 ,  G06F12/1009 ,  G06F12/0871 ,  G06F12/127

摘要： An apparatus and method for page table management. For example, one embodiment of an apparatus comprises: a memory management circuit to perform address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory; a cache to reserve a first cache line containing the base page directory address stored in a modified state; cache snoop circuitry to detect a read to the base page directory address by a processor or graphics processing unit (GPU); and locking circuitry to assert a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.

公开(公告)号：US20180329815A1

公开(公告)日：2018-11-15

申请号：US15590789

申请日：2017-05-09

申请人： Western Digital Technologies, Inc.

发明人： Seung-hwan Song ,  Won Ho Choi ,  Chao Sun ,  Dejan Vucinic

IPC分类号： G06F12/02 ,  G06F12/0831 ,  G06F12/127 ,  G06F13/16 ,  G11C16/04

CPC分类号： G06F12/0246 ,  G06F12/02 ,  G06F12/0215 ,  G06F12/0833 ,  G06F12/127 ,  G06F13/1689 ,  G11C5/04 ,  G11C7/00 ,  G11C8/12 ,  G11C16/0441

摘要： A storage system is provided comprising a controller and a memory comprising a plurality of tiles of memory organized in a plurality of tile groups, wherein a given tile group is busy when any tile in the given tile group is busy. The controller is configured to: inform the host of the busy status of the plurality of tile groups; receive a plurality of commands from the host, wherein each command is provided with a different tile group identifier of a tile group that is not busy; and execute the plurality of commands, wherein because each command comprises a different tile group identifier of a tile group that is not busy, the plurality of commands are executed in parallel.

公开(公告)号：US10049050B2

公开(公告)日：2018-08-14

申请号：US15219068

申请日：2016-07-25

申请人： International Business Machines Corporation

发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Bernhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0879 ,  G06F12/0802 ,  G06F12/127 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0804 ,  G06F12/0891

摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

公开(公告)号：US10001922B2

公开(公告)日：2018-06-19

申请号：US15048043

申请日：2016-02-19

申请人： International Business Machines Corporation

发明人： Mario Blaum ,  Steven R. Hetzler ,  Wayne C. Hineman ,  Robert M. Rees

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/127 ,  G06F12/06 ,  G06F12/02 ,  G06F12/121

CPC分类号： G06F3/0604 ,  G06F3/0619 ,  G06F3/062 ,  G06F3/0638 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/067 ,  G06F3/0686 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/127

摘要： A data storage structure, comprising: a plurality of storage units, each comprising: a storage media; and a library executive configured to manage the storage media. The structure further comprises a buffer connected to a controller, the controller comprising: a host interface configured to receive the instruction from the host machine; an object aggregator configured to combine the plurality of data objects into a data segment; a persistent write buffer configured to store the data segment; a persistent map configured to identify a location of each of the plurality of objects in the data segment; an erasure coder configured to encode the data segment into an erasure code; a destager configured to transfer the data segment from the persistent write buffer to the storage media in a given storage unit; and a library controller configured to communicate with the library executive in the given storage unit.

公开(公告)号：US09933954B2

公开(公告)日：2018-04-03

申请号：US14886215

申请日：2015-10-19

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Perry H. Pelley ,  Anirban Roy

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/127 ,  G06F12/06

CPC分类号： G06F3/0613 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0646 ,  G06F12/127 ,  G06F13/1668 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C2207/229

摘要： A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.

公开(公告)号：US09817764B2

公开(公告)日：2017-11-14

申请号：US14891331

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： Rodney E. Hooker ,  Douglas R. Reed ,  John Michael Greer ,  Colin Eddy

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/0862 ,  G06F9/45 ,  G06F12/0846 ,  G06F9/345 ,  G06F9/38 ,  G06F12/127 ,  G06F12/0811

CPC分类号： G06F12/0862 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/127 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/6026

摘要： A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.

公开(公告)号：US09740623B2

公开(公告)日：2017-08-22

申请号：US13993034

申请日：2013-03-15

申请人： Intel Corporation

发明人： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M Yoo ,  Ganesh Bikshandi

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/127

CPC分类号： G06F12/0891 ,  G06F12/023 ,  G06F12/127 ,  Y02D10/13

摘要： A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.