公开(公告)号：US20220191041A1

公开(公告)日：2022-06-16

申请号：US17119149

申请日：2020-12-11

Applicant: International Business Machines Corporation

Inventor： Adrian C. Gerhard ,  Matthew Vaught

IPC: H04L9/32 ,  H04L9/06 ,  G06F21/62

Abstract: A device receives an access-key package. The access-key package comprises a signature. The device obtains a validation package. The validation package comprises a validation device ID and validation timestamp. The device validates the signature in the access-key package. The device also obtains an updated timestamp. The device then compares the validation timestamp to the updated timestamp.

公开(公告)号：US10467150B2

公开(公告)日：2019-11-05

申请号：US15981163

申请日：2018-05-16

Applicant: International Business Machines Corporation

Inventor： Joseph R. Edwards ,  Robert Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/00 ,  G06F12/1009 ,  G06F3/06

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

公开(公告)号：US20190095337A1

公开(公告)日：2019-03-28

申请号：US16203887

申请日：2018-11-29

Applicant: International Business Machines Corporation

Inventor： Clark A. Anderson ,  Adrian C. Gerhard ,  William J. Maitland, JR.

IPC: G06F12/0871 ,  G06F12/0811 ,  G06F12/0831

Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.

公开(公告)号：US10169605B2

公开(公告)日：2019-01-01

申请号：US15809955

申请日：2017-11-10

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Adrian C. Gerhard ,  Daniel F. Moertl

IPC: G06F21/00 ,  G06F21/62 ,  G06F21/44 ,  G06F21/80 ,  G06F21/85 ,  H04L29/06

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization model processing in Coherent Accelerator Processor Interface (CAPI) adapters. The CAPI adapter includes an authorization table and a file system authorization function to authenticate data access for a client at an extent granularity and to prevent an application from accessing unauthorized data in the CAPI adapter. Each authorization table entry provides for the CAPI client, a CAPI client identification (ID), a CAPI server register space assigning resource ownership to the CAPI client with a CAPI set of allowed functions.

公开(公告)号：US10169241B2

公开(公告)日：2019-01-01

申请号：US15198048

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Clark A. Anderson ,  Adrian C. Gerhard ,  William J. Maitland, Jr.

IPC: G06F12/0811 ,  G06F12/0831 ,  G06F12/0871

Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.

公开(公告)号：US10078595B2

公开(公告)日：2018-09-18

申请号：US15822189

申请日：2017-11-26

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/123 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F11/1076 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/286 ,  G06F2212/312 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940253B2

公开(公告)日：2018-04-10

申请号：US14939838

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

公开(公告)号：US09940252B2

公开(公告)日：2018-04-10

申请号：US14939762

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

公开(公告)号：US09940249B2

公开(公告)日：2018-04-10

申请号：US14939516

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

公开(公告)号：US09904795B2

公开(公告)日：2018-02-27

申请号：US15457229

申请日：2017-03-13

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Adrian C. Gerhard ,  Daniel F. Moertl

IPC: G06F21/00 ,  G06F21/62 ,  G06F21/60 ,  G06F9/455 ,  G06F12/14

CPC classification number: G06F3/062 ,  G06F3/0637 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/45558 ,  G06F12/1425 ,  G06F13/382 ,  G06F21/53 ,  G06F21/604 ,  G06F21/6218 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/1052 ,  G06F2221/2141

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.