公开(公告)号：US10467150B2

公开(公告)日：2019-11-05

申请号：US15981163

申请日：2018-05-16

Applicant: International Business Machines Corporation

Inventor： Joseph R. Edwards ,  Robert Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/00 ,  G06F12/1009 ,  G06F3/06

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

公开(公告)号：US10078595B2

公开(公告)日：2018-09-18

申请号：US15822189

申请日：2017-11-26

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/123 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F11/1076 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/286 ,  G06F2212/312 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940253B2

公开(公告)日：2018-04-10

申请号：US14939838

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

公开(公告)号：US09940252B2

公开(公告)日：2018-04-10

申请号：US14939762

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

公开(公告)号：US09940249B2

公开(公告)日：2018-04-10

申请号：US14939516

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

公开(公告)号：US09864695B2

公开(公告)日：2018-01-09

申请号：US14940035

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0895 ,  G06F12/0868 ,  G06F12/122 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09798493B2

公开(公告)日：2017-10-24

申请号：US14106890

申请日：2013-12-16

Applicant: International Business Machines Corporation

Inventor： Shawn P. Authement ,  Christopher M. Dennett ,  Gowrisankar Radhakrishnan ,  Donald J. Ziebarth

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F2003/0697

Abstract: An interface receives a command corresponding to a non-volatile memory. The interface determines whether a bypass mode is enabled and whether the command is a medium-access command. A primary processing node processes the command in response to determining at least one of the following: that the bypass mode is disabled or that the command is not a medium-access command. A secondary processing node processes the command, in response to determining that the bypass mode is enabled and that the command is a medium-access command.

公开(公告)号：US10067880B2

公开(公告)日：2018-09-04

申请号：US15055770

申请日：2016-02-29

Applicant: International Business Machines Corporation

Inventor： Joseph R. Edwards ,  Robert Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/00 ,  G06F12/1009 ,  G06F3/06

Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.

公开(公告)号：US09940258B2

公开(公告)日：2018-04-10

申请号：US14940050

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940255B2

公开(公告)日：2018-04-10

申请号：US14939961

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.