公开(公告)号：US10942659B2

公开(公告)日：2021-03-09

申请号：US16429871

申请日：2019-06-03

Applicant: International Business Machines Corporation

Inventor： Daniel F. Moertl ,  Andrew K. Martin ,  Damir A. Jamsek ,  Robert E. Galbraith ,  Rick A. Weckwerth

IPC: G06F3/06 ,  G06F12/02

Abstract: Techniques for persisting a logical address-to-virtual address table in a solid state storage device are presented. An example method includes receiving a request to write data to a logical block address (LBA) in a memory component of the solid state storage device. The data is written to a location identified by a virtual block address (VBA) in the solid state storage device. The VBA is stored in a rotating dump table in a reserved logical unit of the solid state storage device. A mapping between the LBA and the VBA is stored in a rotating journal table located in the reserved logical unit. The rotating journal table is buffered such that a number of journal entries are stored in a buffer until a threshold number of journal entries are committed to the rotating journal table. A pointer to a current address in the rotating journal is stored in the buffer.

公开(公告)号：US10552243B2

公开(公告)日：2020-02-04

申请号：US15782119

申请日：2017-10-12

Applicant: International Business Machines Corporation

Inventor： Roman A. Pletka ,  Timothy J. Fisher ,  Robert E. Galbraith ,  Kevin E. Sallese ,  Christopher M. Dennett

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G11B20/18

Abstract: Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A “corrective DPL” corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the “initial DPL level”), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.

公开(公告)号：US10078595B2

公开(公告)日：2018-09-18

申请号：US15822189

申请日：2017-11-26

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/123 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F11/1076 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/286 ,  G06F2212/312 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940253B2

公开(公告)日：2018-04-10

申请号：US14939838

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

公开(公告)号：US09940252B2

公开(公告)日：2018-04-10

申请号：US14939762

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

公开(公告)号：US09940249B2

公开(公告)日：2018-04-10

申请号：US14939516

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

公开(公告)号：US09864695B2

公开(公告)日：2018-01-09

申请号：US14940035

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0895 ,  G06F12/0868 ,  G06F12/122 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940258B2

公开(公告)日：2018-04-10

申请号：US14940050

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US09940255B2

公开(公告)日：2018-04-10

申请号：US14939961

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

公开(公告)号：US09658968B1

公开(公告)日：2017-05-23

申请号：US14939254

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/128 ,  G06F12/122 ,  G06F12/0806 ,  G06F3/06

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.