公开(公告)号：US11914726B2

公开(公告)日：2024-02-27

申请号：US16520290

申请日：2019-07-23

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F21/62 ,  G06F9/455

CPC分类号： G06F21/6209 ,  G06F9/45558 ,  G06F2009/45583

摘要： Systems, apparatuses, and methods related to a processor having configurable permission data for controlling access to a register of the processor from instructions running in different domains are described. Instructions can be used in predefined execution domains, such as hypervisor, operating system, application, etc. Different permission bits can be set for instructions running in different domains. In response to an instruction executed in the processor generates a request to access the register, the processor is configured to determine whether to accept or reject the request based on a permission bit provided in the permission data corresponding to an execution domain in which the instruction is running.

公开(公告)号：US11507374B2

公开(公告)日：2022-11-22

申请号：US16417495

申请日：2019-05-20

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/30 ,  G06F15/80

摘要： Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of comparison operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors.

公开(公告)号：US20220350609A1

公开(公告)日：2022-11-03

申请号：US17866868

申请日：2022-07-18

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/38 ,  G06F21/71 ,  G06F9/50

摘要： Methods, systems, and apparatuses related to re-order buffers and for protection from timing-based security attacks are described. A processor may have functional units configured to execute instructions out of order, a re-order buffer configured to buffer the execution results of instructions for output in order, and a controller configured to randomize data timing in the re-order buffer. For example, the controller can make random adjustments to the capacity of the re-order buffer in buffering and/or sorting execution results and thus randomize data timing in the re-order buffer.

公开(公告)号：US11481221B2

公开(公告)日：2022-10-25

申请号：US16029135

申请日：2018-07-06

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A computing device (e.g., a processor) having a plurality of branch target buffers. A first branch target buffer in the plurality of branch target buffers is used in execution of a set of instructions containing a call to a subroutine. In response to the call to the subroutine, a second branch target buffer is allocated from the plurality of branch target buffers for execution of instructions in the subroutine. The second branch target buffer is cleared before the execution of the instructions in the subroutine. The execution of the instructions in the subroutine is restricted to access the second branch target buffer and blocked from accessing branch target buffers other than the second branch target buffer.

公开(公告)号：US20220121576A1

公开(公告)日：2022-04-21

申请号：US17563985

申请日：2021-12-28

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F12/0842

摘要： A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.

公开(公告)号：US20210374289A1

公开(公告)日：2021-12-02

申请号：US17393248

申请日：2021-08-03

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F21/74 ,  G06F21/72 ,  G06F9/30 ,  G06F12/1036 ,  G06F21/60

摘要： Methods, systems, and apparatuses related to adjustable security levels in processors are described. A processor may have functional units and a register configured to control security operations of the functional units. The register configures the functional units to operate in a first mode of security operations when the register contains a first setting; and the register configures the functional units to operate in a second mode of security operations when the register contains a second setting (e.g., to skip/bypassing a set of security operation circuit for enhanced execution speed).

公开(公告)号：US20210263843A1

公开(公告)日：2021-08-26

申请号：US17315076

申请日：2021-05-07

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F12/02

摘要： A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.

公开(公告)号：US20210149675A1

公开(公告)日：2021-05-20

申请号：US17158999

申请日：2021-01-26

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0842

摘要： A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

公开(公告)号：US20210141742A1

公开(公告)日：2021-05-13

申请号：US17154722

申请日：2021-01-21

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F12/14 ,  G06F12/10 ,  G06F21/53

摘要： Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.

公开(公告)号：US10949210B2

公开(公告)日：2021-03-16

申请号：US16028930

申请日：2018-07-06

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F12/0891

摘要： A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.