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    Graph caching
    1.
    发明授权
    Graph caching 有权

    公开(公告)号：US09787693B2

    公开(公告)日：2017-10-10

    申请号：US13311244

    申请日：2011-12-05

    Applicant: Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

    Inventor： Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

    IPC: G06F17/30 ,  H04L29/06 ,  G06F9/44

    CPC classification number: H04L63/1408 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

    Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

    Regular expression processing automaton
    2.
    发明授权
    Regular expression processing automaton 有权
    正则表达式处理自动机

    公开(公告)号：US09398033B2

    公开(公告)日：2016-07-19

    申请号：US13168395

    申请日：2011-06-24

    Applicant: Rajan Goyal ,  Lakshmipathi Billa

    Inventor： Rajan Goyal ,  Lakshmipathi Billa

    IPC: H04L29/06

    CPC classification number: H04L63/1416 ,  H04L63/168 ,  H04L69/12

    Abstract: A method and corresponding apparatus are provided implementing a stage one of run time processing using Deterministic Finite Automata (DFA) and implementing a stage two of run time processing using Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload, such as the payload portion of an Internet Protocol (IP) datagram, or an input stream.

    Abstract translation: 提供了一种使用确定性有限自动机（DFA）实现运行时间处理的第一阶段并且使用非确定性有限自动机（NFA）实现运行时处理的第二阶段来查找有效载荷中的模式的存在的方法和相应装置 ，例如因特网协议（IP）数据报的有效载荷部分或输入流。

    Reverse NFA generation and processing
    3.
    发明授权
    Reverse NFA generation and processing 有权
    逆向NFA生成和处理

    公开(公告)号：US09203805B2

    公开(公告)日：2015-12-01

    申请号：US13303885

    申请日：2011-11-23

    Applicant: Rajan Goyal ,  Satyanarayana Lakshmipathi Billa

    Inventor： Rajan Goyal ,  Satyanarayana Lakshmipathi Billa

    IPC: G06F21/00 ,  H04L29/06

    CPC classification number: H04L63/0254 ,  G06F17/30958 ,  H04L63/0245 ,  H04L63/1408 ,  H04L63/1416

    Abstract: In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequence of characters associated with the marked node. Generating the rNFA for a given pattern includes inserting processing nodes for processing an input sequence of patterns to determine a match for the given pattern. In addition, the rNFA is generated from the given type of pattern.

    Abstract translation: 在安全装置的处理器中，字符序列的输入通过为至少一个给定模式生成的有限自动机图。 在有限自动机图的标记节点处，如果在标记节点处匹配至少一个给定模式的特定类型，则通过针对该标记节点生成的反向非确定性有限自动机（rNFA）图来处理输入的字符序列 通过从与所标记的节点相关联的输入字符序列的偏移开始的rNFA向后移动输入的字符序列来指定至少一个给定模式的特定类型。 为给定模式生成rNFA包括插入用于处理输入模式序列的处理节点以确定给定模式的匹配。 此外，rNFA是从给定类型的模式生成的。

    System and method to reduce memory access latencies using selective replication across multiple memory ports
    6.
    发明授权
    System and method to reduce memory access latencies using selective replication across multiple memory ports 有权
    使用多个内存端口选择性复制来减少内存访问延迟的系统和方法

    公开(公告)号：US08560757B2

    公开(公告)日：2013-10-15

    申请号：US13280738

    申请日：2011-10-25

    Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    IPC: G06F12/00

    CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

    Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

    Abstract translation: 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

    SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS
    8.
    发明申请
    SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS 有权
    使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法

    公开(公告)号：US20130103904A1

    公开(公告)日：2013-04-25

    申请号：US13280738

    申请日：2011-10-25

    Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    IPC: G06F12/10 ,  G06F12/00

    CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

    Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

    Abstract translation: 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

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