公开(公告)号：US08086609B2

公开(公告)日：2011-12-27

申请号：US11982391

申请日：2007-11-01

Applicant: Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

Inventor： Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

IPC: G06F17/30

CPC classification number: H04L63/1408 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

Abstract translation: 在用于分析确定性有限自动机（DFA）的节点的方法和装置中，可以确定基于DFA图形几何配置的可访问性排序，以便确定DFA图形的可缓存部分，以减少外部数量 内存访问 步行者进程可以被配置为在图形缓存以及主存储器中走图。 可以以允许每个弧包括其指向的节点被存储在图形高速缓存或主存储器中的信息的方式生成图。 步行者可以使用该信息来确定是否访问图形缓存或主存储器中的下一个弧。

公开(公告)号：US20090119279A1

公开(公告)日：2009-05-07

申请号：US11982391

申请日：2007-11-01

Applicant: Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

Inventor： Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

IPC: G06F17/30

CPC classification number: H04L63/1408 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

Abstract translation: 在用于分析确定性有限自动机（DFA）的节点的方法和装置中，可以确定基于DFA图形几何配置的可访问性排序，以便确定DFA图形的可缓存部分，以减少外部数量 内存访问 步行者进程可以被配置为在图形缓存以及主存储器中走图。 可以以允许每个弧包括其指向的节点被存储在图形高速缓存或主存储器中的信息的方式生成图。 步行者可以使用该信息来确定是否访问图形缓存或主存储器中的下一个弧。

公开(公告)号：US20120143854A1

公开(公告)日：2012-06-07

申请号：US13311244

申请日：2011-12-05

Applicant: Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

Inventor： Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

IPC: G06F17/30

CPC classification number: H04L63/1408 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

Abstract translation: 在用于分析确定性有限自动机（DFA）的节点的方法和装置中，可以确定基于DFA图形几何配置的可访问性排序，以便确定DFA图形的可缓存部分，以减少外部数量 内存访问 步行者进程可以被配置为在图形缓存以及主存储器中走图。 可以以允许每个弧包括其指向的节点被存储在图形高速缓存或主存储器中的信息的方式生成图。 步行者可以使用该信息来确定是否访问图形缓存或主存储器中的下一个弧。

公开(公告)号：US09787693B2

公开(公告)日：2017-10-10

申请号：US13311244

申请日：2011-12-05

Applicant: Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

Inventor： Rajan Goyal ,  Muhammad Raghib Hussain ,  Trent Parker

IPC: G06F17/30 ,  H04L29/06 ,  G06F9/44

CPC classification number: H04L63/1408 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

公开(公告)号：US08560475B2

公开(公告)日：2013-10-15

申请号：US11224728

申请日：2005-09-12

Applicant: Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

Inventor： Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

IPC: G06F17/00

CPC classification number: G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

Abstract translation: 改进的内容搜索机制使用包括智能节点的图避免了后处理的开销，并提高了内容处理应用的整体性能。 智能节点类似于DFA图中的节点，但包含一个命令。 智能节点中的命令允许生成和检查节点的附加状态。 这种附加状态允许内容搜索机制以两种不同的解释遍历相同的节点。 通过生成节点的状态，节点的图形不会变成指数。 它还允许在到达节点时调用用户功能，节点可以执行任何所需的用户任务，包括修改输入数据或位置。

公开(公告)号：US20120011373A1

公开(公告)日：2012-01-12

申请号：US13090882

申请日：2011-04-20

Applicant: Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

Inventor： Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

IPC: G06F12/14

CPC classification number: G06F21/10 ,  G06F2221/0704

Abstract: Disclosed are systems and methods for protecting secret device keys, such as High-bandwidth Digital Content Protection (HDCP) device keys. Instead of storing secret device keys in the plain, a security algorithm and one or more protection keys are stored on the device. The security algorithm is applied to the secret device keys and the one or more protection keys to produce encrypted secret device keys. The encrypted secret device keys are then stored either on chip or off-chip.

Abstract translation: 公开了用于保护秘密设备密钥的系统和方法，例如高带宽数字内容保护（HDCP）设备密钥。 代替将秘密设备密钥存储在平原中，安全算法和一个或多个保护密钥被存储在设备上。 安全算法被应用于秘密设备密钥和一个或多个保护密钥以产生加密的秘密设备密钥。 然后将加密的秘密设备密钥存储在芯片上或芯片外。

公开(公告)号：US20060059286A1

公开(公告)日：2006-03-16

申请号：US11042476

申请日：2005-01-25

Applicant: Michael Bertone ,  David Carlson ,  Richard Kessler ,  Philip Dickinson ,  Muhammad Hussain ,  Trent Parker

Inventor： Michael Bertone ,  David Carlson ,  Richard Kessler ,  Philip Dickinson ,  Muhammad Hussain ,  Trent Parker

IPC: G06F13/24

CPC classification number: G06F12/084 ,  G06F9/30014 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/3824 ,  G06F9/383 ,  G06F11/3632 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/24 ,  G06F2212/6012 ,  G06F2212/6022

Abstract: In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

Abstract translation: 在多核处理器中，高速中断信号互连允许多个处理器在同一时间被中断。 例如，全局信号互连耦合到多个处理器中的每一个，每个处理器被配置为选择性地提供中断信号或其上的脉冲。 优选地，每个处理器内核能够在每个时钟周期期间脉冲全局信号互连以最小化触发事件与其各自的中断信号之间的延迟。 多个处理器中的每一个还优选地在提供脉冲的相同周期内感测或采样全局信号互连，以确定中断信号的存在。 在感测到中断信号时，多个处理器中的每一个基本上同时响应。 例如，由多个处理器中的每一个采样的中断信号使每个处理器调用调试处理程序。

公开(公告)号：US20060085533A1

公开(公告)日：2006-04-20

申请号：US11224728

申请日：2005-09-12

Applicant: Muhammad Hussain ,  David Carlson ,  Gregg Bouchard ,  Trent Parker

Inventor： Muhammad Hussain ,  David Carlson ,  Gregg Bouchard ,  Trent Parker

IPC: G06F15/173

CPC classification number: G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

Abstract translation: 改进的内容搜索机制使用包括智能节点的图避免了后处理的开销，并提高了内容处理应用的整体性能。 智能节点类似于DFA图中的节点，但包含一个命令。 智能节点中的命令允许生成和检查节点的附加状态。 这种附加状态允许内容搜索机制以两种不同的解释遍历相同的节点。 通过生成节点的状态，节点的图形不会变成指数。 它还允许在到达节点时调用用户功能，节点可以执行任何所需的用户任务，包括修改输入数据或位置。

公开(公告)号：US08661266B2

公开(公告)日：2014-02-25

申请号：US13090882

申请日：2011-04-20

Applicant: Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

Inventor： Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

IPC: G06F11/30

CPC classification number: G06F21/10 ,  G06F2221/0704

Abstract: Disclosed are systems and methods for protecting secret device keys, such as High-bandwidth Digital Content Protection (HDCP) device keys. Instead of storing secret device keys in the plain, a security algorithm and one or more protection keys are stored on the device. The security algorithm is applied to the secret device keys and the one or more protection keys to produce encrypted secret device keys. The encrypted secret device keys are then stored either on chip or off-chip.

Abstract translation: 公开了用于保护秘密设备密钥的系统和方法，例如高带宽数字内容保护（HDCP）设备密钥。 代替将秘密设备密钥存储在平原中，安全算法和一个或多个保护密钥被存储在设备上。 安全算法被应用于秘密设备密钥和一个或多个保护密钥以产生加密的秘密设备密钥。 然后将加密的秘密设备密钥存储在芯片上或芯片外。