公开(公告)号：US20240078202A1

公开(公告)日：2024-03-07

申请号：US17929946

申请日：2022-09-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Pankaj DESHMUKH ,  Shyamkumar THOZIYOOR ,  Subbarao PALACHARLA

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0623

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

公开(公告)号：US20230359380A1

公开(公告)日：2023-11-09

申请号：US18352813

申请日：2023-07-14

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/064 ,  G06F3/0679 ,  G06F3/0659 ,  G06F9/5016 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1668 ,  G06F3/0614 ,  G06F2212/7202

Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

公开(公告)号：US11748012B2

公开(公告)日：2023-09-05

申请号：US17720399

申请日：2022-04-14

Applicant: KIOXIA CORPORATION

Inventor： Shinichi Kanno

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/064 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1668 ,  G06F2212/7202

Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

公开(公告)号：US20180307423A1

公开(公告)日：2018-10-25

申请号：US16024009

申请日：2018-06-29

Applicant: SOCIONEXT INC.

Inventor： Yoshihiro TAKEMAE

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04 ,  G06F12/02 ,  G06F13/16 ,  G06F12/06 ,  G06F12/00

CPC classification number: G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

公开(公告)号：US20180277176A1

公开(公告)日：2018-09-27

申请号：US15795453

申请日：2017-10-27

Applicant: SK hynix Inc.

Inventor： Sok-Kyu LEE

IPC: G11C7/10 ,  G06F13/16 ,  G11C8/06 ,  G06F12/06

CPC classification number: G11C7/1015 ,  G06F12/0623 ,  G06F13/1673 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0441 ,  G11C16/0483 ,  G11C16/26

Abstract: A memory system includes: a memory device; and a controller suitable for controlling the memory device to perform a serial read operation by providing a serial read command and a start physical address for the serial read command when an external read command includes a request for the serial read operation, the serial read command includes consecutive physical address numbers information, in response to the serial read command, the memory device sets a read bias, reads data stored therein with the set read bias according to the start physical address and the consecutive physical address numbers information, and then discharges the read bias.

公开(公告)号：US20180196767A1

公开(公告)日：2018-07-12

申请号：US15867646

申请日：2018-01-10

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/06 ,  G11C7/20 ,  G11C7/10 ,  G06F12/02 ,  G11C7/22

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1678 ,  G06F2212/7206 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20180165192A1

公开(公告)日：2018-06-14

申请号：US15877876

申请日：2018-01-23

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Grant R. Wallace ,  Philip N. Shilane

IPC: G06F12/06 ,  G06F9/54 ,  G06F13/16

CPC classification number: G06F12/0623 ,  G06F9/544 ,  G06F13/1663 ,  G06F2212/251

Abstract: Systems and methods for writing data are provided. A lock-free container and methods of writing to the lock-free container are disclosed. The container is associated with a tail pointer that identifies free space in the container. Threads writing to the container access the tail pointer and update an offset in the tail pointer to account for a size of a write to the container. Multiple threads can write to the same container without having to contend for a container lock.

公开(公告)号：US09990282B2

公开(公告)日：2018-06-05

申请号：US15140333

申请日：2016-04-27

Applicant: Oracle International Corporation

Inventor： Joseph Wright ,  Erik Michael Schlanger ,  Eric DeVolder

IPC: G06F12/06

CPC classification number: G06F12/0623 ,  G06F2212/1041

Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

公开(公告)号：US20180089079A1

公开(公告)日：2018-03-29

申请号：US15273743

申请日：2016-09-23

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Wendy Arnott ELSASSER ,  Michael Andrew CAMPBELL

IPC: G06F12/06 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0888

CPC classification number: G06F12/0623 ,  G06F12/084 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/4234 ,  G06F2212/6046 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

公开(公告)号：US09921763B1

公开(公告)日：2018-03-20

申请号：US14750293

申请日：2015-06-25

Applicant: Crossbar, Inc.

Inventor： Cliff Zitlaw

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/06

CPC classification number: G06F3/0619 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0623 ,  G06F2003/0692 ,  G06F2212/2532 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/12 ,  G11C13/00

Abstract: Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.