公开(公告)号：US20240320175A1

公开(公告)日：2024-09-26

申请号：US18588277

申请日：2024-02-27

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya OOBA

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/30

CPC classification number: G06F13/362 ,  G06F13/1678 ,  G06F13/30

Abstract: A semiconductor device capable of suppressing reduction in performance is provided. The semiconductor device includes: a processor; a DR processor including a DMA controller; a system memory; an internal bus to which the processor, the DR processor, and the system memory are connected; and a bus arbiter connected to the processor and the DR processor, the bus arbiter executing arbitration between access to the system memory by the processor and access to the system memory by the DMA controller in accordance with a predetermined priority order. Here, the DR processor includes a frequency circuit determining a frequency at which the access to the system memory by the DMA controller is not permitted by the arbitration made by the bus arbiter.

公开(公告)号：US20240273039A1

公开(公告)日：2024-08-15

申请号：US18589259

申请日：2024-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11947474B2

公开(公告)日：2024-04-02

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20230342313A1

公开(公告)日：2023-10-26

申请号：US18215732

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Przemek Guzy ,  Sheran Cardoza ,  Shan Liu

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1631

Abstract: An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.

公开(公告)号：US11755507B2

公开(公告)日：2023-09-12

申请号：US17744331

申请日：2022-05-13

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F13/16 ,  H04L12/863 ,  G06F9/48 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G06F13/1673 ,  G06F9/4881 ,  G06F13/1678 ,  G06F13/4059 ,  G11C11/4076 ,  G11C11/4094 ,  G06F2209/486 ,  G06F2209/5018

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20190163650A1

公开(公告)日：2019-05-30

申请号：US16006082

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghyun KIM ,  Ki-Seok OH

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1678 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/4068 ,  G11C7/1075 ,  H01L25/0657 ,  H01L2225/06541

Abstract: An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.

公开(公告)号：US20190095366A1

公开(公告)日：2019-03-28

申请号：US15713100

申请日：2017-09-22

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA TEC KABUSHIKI KAISHA

Inventor： Tsutomu UETA

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/1694 ,  G06F13/4295 ,  G06F2213/0026

Abstract: A data transfer control device includes an acquisition section, an analysis section, a band detection section, a mask output section and a selection section. The acquisition section acquires data from a plurality of processing sections for transmitting the data with a transmission path. The analysis section analyzes additional information of the data acquired by the acquisition section. The band detection section detects a transmission band of the transmission path based on the additional information. The mask output section outputs a request mask signal for suppressing the transmission of the data based on the transmission band detected by the band detection section and a target band preset on the transmission path. The selection section selects the data transmitted by the processing section based on the request mask signal output by the mask output section.

公开(公告)号：US20180276167A1

公开(公告)日：2018-09-27

申请号：US15543207

申请日：2015-01-29

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Peter Seiler ,  Shane Ward ,  Byron A. Alcorn ,  Raphael Gay

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1668 ,  G06F13/1678

Abstract: An apparatus includes a memory card that includes at least one memory module and an expansion connector to connect with at least one expansion memory card. A lane distributor on the memory card interfaces with a set of bidirectional lanes and provides a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module and the expansion memory card via the expansion connector.

公开(公告)号：US10073619B2

公开(公告)日：2018-09-11

申请号：US15842295

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F13/40 ,  G11C5/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US20180217837A1

公开(公告)日：2018-08-02

申请号：US15925957

申请日：2018-03-20

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F9/3013 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3877 ,  G06F9/3889 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.