Invention Application
US20130103904A1 SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS
有权
使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法
- Patent Title: SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS
- Patent Title (中): 使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法
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Application No.: US13280738Application Date: 2011-10-25
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Publication No.: US20130103904A1Publication Date: 2013-04-25
- Inventor: Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler
- Applicant: Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler
- Applicant Address: US CA San Jose
- Assignee: Cavium, Inc.
- Current Assignee: Cavium, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/00

Abstract:
In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
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