公开(公告)号：US20130103909A1

公开(公告)日：2013-04-25

申请号：US13280756

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/08 ,  G06F12/0831

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract translation: 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访​​问路径和到存储器的旁路高速缓存访​​问路径，接收从旁路高速缓存访​​问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访​​问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访​​问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。

公开(公告)号：US08560757B2

公开(公告)日：2013-10-15

申请号：US13280738

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

IPC: G06F12/00

CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract translation: 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

公开(公告)号：US20130103904A1

公开(公告)日：2013-04-25

申请号：US13280738

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract translation: 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

公开(公告)号：US08850125B2

公开(公告)日：2014-09-30

申请号：US13280756

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/08 ,  G06F12/0831

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract translation: 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访​​问路径和到存储器的旁路高速缓存访​​问路径，接收从旁路高速缓存访​​问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访​​问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访​​问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。