公开(公告)号：US07594081B2

公开(公告)日：2009-09-22

申请号：US11024002

申请日：2004-12-28

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

公开(公告)号：US07558925B2

公开(公告)日：2009-07-07

申请号：US11335189

申请日：2006-01-18

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

IPC: G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0653 ,  G06F2212/174

Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

Abstract translation: 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

公开(公告)号：US08392590B2

公开(公告)日：2013-03-05

申请号：US11221408

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F17/28

CPC classification number: H04L49/90 ,  G06F15/7846 ,  H04L29/06 ,  H04L63/02 ,  H04L63/04 ,  H04L63/145 ,  H04L63/164 ,  H04L69/12

Abstract: A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

Abstract translation: 用于实时传入传入分组数据的运行确定性有限自动机（DFA）图的处理器。 所述处理器包括至少一个处理器核心和与所述至少一个处理器核心异步操作的DFA模块，用于使用存储在高速缓存相干存储器中的分组数据遍历存储在非高速缓冲存储器中的至少一个DFA图形。

公开(公告)号：US08301788B2

公开(公告)日：2012-10-30

申请号：US11220899

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F15/173 ,  H04L12/28 ,  H04J3/06

CPC classification number: G06F9/30003 ,  H04L1/0045

Abstract: A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

Abstract translation: 描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。 该指令包括一个或多个预定义字段。 其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。 另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。 另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。 这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

公开(公告)号：US06954770B1

公开(公告)日：2005-10-11

申请号：US09938166

申请日：2001-08-23

Applicant: David A. Carlson ,  Gregg A. Bouchard ,  Anand Varadharajan ,  Derek S. Brasili

Inventor： David A. Carlson ,  Gregg A. Bouchard ,  Anand Varadharajan ,  Derek S. Brasili

IPC: G06F1/02 ,  G06F7/58

CPC classification number: G06F7/588 ,  G06F7/582 ,  H04L9/0869

Abstract: A random number generator comprising an oscillator with an output signal dependant upon a random source, a sampling device to sample the output signal from the oscillator to obtain a sampled oscillator output, and a fixed frequency clock driven linear feedback shift register (LFSR) communicatively coupled to the sampling device via a digital gate to receive the sampled oscillator output, and to provide a random number at an output of the LFSR. Additionally, the random number generator may comprise an optional mixing function communicatively coupled to the LFSR to read the random number, and to insert the random number into an algorithm to obtain a robust random number.

Abstract translation: 一种随机数发生器，包括具有取决于随机源的输出信号的振荡器，用于对来自振荡器的输出信号进行采样以获得采样的振荡器输出的采样装置以及通信耦合的固定频率时钟驱动的线性反馈移位寄存器（LFSR） 通过数字门到采样装置接收采样的振荡器输出，并在LFSR的输出端提供随机数。 此外，随机数生成器可以包括通信地耦合到LFSR以读取随机数的可选混合功能，并将随机数插入到算法中以获得鲁棒的随机数。

公开(公告)号：US08560475B2

公开(公告)日：2013-10-15

申请号：US11224728

申请日：2005-09-12

Applicant: Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

Inventor： Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

IPC: G06F17/00

CPC classification number: G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

Abstract translation: 改进的内容搜索机制使用包括智能节点的图避免了后处理的开销，并提高了内容处理应用的整体性能。 智能节点类似于DFA图中的节点，但包含一个命令。 智能节点中的命令允许生成和检查节点的附加状态。 这种附加状态允许内容搜索机制以两种不同的解释遍历相同的节点。 通过生成节点的状态，节点的图形不会变成指数。 它还允许在到达节点时调用用户功能，节点可以执行任何所需的用户任务，包括修改输入数据或位置。

公开(公告)号：US08356194B2

公开(公告)日：2013-01-15

申请号：US12695648

申请日：2010-01-28

Applicant: David A. Carlson ,  Richard E. Kessler ,  Amer Haider

Inventor： David A. Carlson ,  Richard E. Kessler ,  Amer Haider

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F11/3058 ,  Y02D10/24 ,  Y10S323/907

Abstract: Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

Abstract translation: 本发明的实施例涉及限制在处理器中发生的最大功率耗散。 因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。 示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

公开(公告)号：US20110185203A1

公开(公告)日：2011-07-28

申请号：US12695648

申请日：2010-01-28

Applicant: David A. Carlson ,  Richard E. Kessler ,  Amer Haider

Inventor： David A. Carlson ,  Richard E. Kessler ,  Amer Haider

IPC: G06F1/00

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F11/3058 ,  Y02D10/24 ,  Y10S323/907

Abstract: Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

Abstract translation: 本发明的实施例涉及限制在处理器中发生的最大功率耗散。 因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。 示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

公开(公告)号：US07941585B2

公开(公告)日：2011-05-10

申请号：US11015343

申请日：2004-12-17

Applicant: David H. Asher ,  David A. Carlson ,  Richard E. Kessler

Inventor： David H. Asher ,  David A. Carlson ,  Richard E. Kessler

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/084 ,  G06F9/30014 ,  G06F9/30138 ,  G06F9/383 ,  G06F11/3632 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/24 ,  G06F2212/6012 ,  G06F2212/6022

Abstract: A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.

Abstract translation: RISC型处理器包括主寄存器文件和数据高速缓存。 可以将数据高速缓存分割成包括本地存储器，当处理器正在执行使用主寄存器文件的指令时，可以在缓存块的基础上动态地改变其大小。 本地存储器可以作为额外的寄存器文件模拟到处理器，并且可以驻留在虚拟地址处。 本地存储器可以被进一步分区以从不可缓存地址预取数据以被存储/加载到主寄存器文件中。

公开(公告)号：US07240203B2

公开(公告)日：2007-07-03

申请号：US10025509

申请日：2001-12-19

Applicant: Richard E. Kessler ,  David A. Carlson ,  Muhammad Raghib Hussain ,  Robert A. Sanzone ,  Khaja E. Ahmed ,  Michael D. Varga

Inventor： Richard E. Kessler ,  David A. Carlson ,  Muhammad Raghib Hussain ,  Robert A. Sanzone ,  Khaja E. Ahmed ,  Michael D. Varga

IPC: H04L9/00

CPC classification number: H04L63/164 ,  G06F21/606

Abstract: A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.

Abstract translation: 描述用于处理安全操作的方法和装置。 在一个实施例中，处理器包括多个执行单元，用于处理多个安全操作请求。 执行单元的数量是基于存储在请求数中的指针，将与多个与远程存储器内的请求数相关联的输出数据结构的请求数的结果输出。 执行单元的数量可以按照与请求队列中的请求顺序不同的顺序输出结果。 处理器还包括耦合到执行单元数量的请求单元。 请求单元从远程存储器中的请求队列中检索一部分请求数，并且从远程存储器中获取部分请求的相关联的输入数据结构。 此外，请求单元是基于执行单元的数量的处理的可用性将检索到的请求分发到执行单元的数量。