公开(公告)号：US06832328B2

公开(公告)日：2004-12-14

申请号：US09850228

申请日：2001-05-08

Applicant: Satoru Kishimoto

Inventor： Satoru Kishimoto

IPC: G06F104

CPC classification number: G06F17/5068

Abstract: An object of the present invention is to enable precise and easy adjustment of clock skew. A clock distribution circuit is designed and the placement and routing of the entire chip including the clock distribution circuit follows. Then the clock skew value is calculated and whether the calculated clock skew exceeds a target value is checked. When the clock skew exceeds the target value, the outputs of some driver elements are disconnected or connected to adjust the clock skew. The steps disconnecting or connecting the outputs of the drivers are repeated until the clock skew becomes equal to or smaller than the target value.

Abstract translation: 本发明的目的是能够精确和容易地调整时钟偏移。 设计时钟分配电路，并且包括包括时钟分配电路在内的整个芯片的放置和布线。 然后计算时钟偏移值，并检查计算出的时钟偏差超过目标值。 当时钟偏移超过目标值时，某些驱动器元件的输出断开或连接以调整时钟偏移。 重复断开或连接驱动器的输出的步骤，直到时钟偏移等于或小于目标值。

公开(公告)号：US06810486B2

公开(公告)日：2004-10-26

申请号：US09818614

申请日：2001-03-28

Applicant: Eyal Fayneh ,  Earnest Knoll

Inventor： Eyal Fayneh ,  Earnest Knoll

IPC: G06F104

CPC classification number: G06F1/10

Abstract: A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.

Abstract translation: 用于相对于第一时钟去偏斜第二和第三时钟的技术包括接收第一时钟并从第一和第二时钟产生第四时钟。 从第四时钟产生第五时钟和第三时钟，第五时钟与第三时钟基本相同。 然后从第五个时钟产生第二个时钟。 所述第四时钟由具有所述第一和第二时钟作为其输入的第一锁相环生成，所述第二时钟由连接到时钟树的第二锁相环产生，所述第二锁相环具有所述第五时钟和所述第二时钟 时钟作为其输入。

公开(公告)号：US06810485B2

公开(公告)日：2004-10-26

申请号：US09755252

申请日：2001-01-04

Applicant: Peter McEwen ,  Ara Patapoutian ,  Ke Han

Inventor： Peter McEwen ,  Ara Patapoutian ,  Ke Han

IPC: G06F104

CPC classification number: G11B20/1403 ,  G11B20/10296 ,  G11B20/1426

Abstract: Determining a phase error in a data signal includes detecting bits in an original data signal, determining a phase error in the original data signal based on the detected bits, adjusting a clock signal based on the phase error, sampling the original data signal with the clock signal to produce a sampled data signal, and repeating detecting, determining, adjusting and sampling using the sampled data signal instead of the original data signal.

Abstract translation: 确定数据信号中的相位误差包括检测原始数据信号中的位，基于检测到的位确定原始数据信号中的相位误差，基于相位误差调整时钟信号，用时钟采样原始数据信号 信号以产生采样数据信号，并且使用采样数据信号代替原始数据信号来重复检测，确定，调整和采样。

公开(公告)号：US06806755B1

公开(公告)日：2004-10-19

申请号：US10412103

申请日：2003-04-10

Applicant: Alan Christopher Simmonds

Inventor： Alan Christopher Simmonds

IPC: G06F104

CPC classification number: G06F1/08

Abstract: A technique for glitchless switching among different frequency input clocks in a circuit includes monitoring each of the clocks and determining when the relative phases of the respective clocks are within a predetermined maximum of phase difference. Once the relative phases of the respective clocks are within an acceptable range, the system switches from one clock to another.

Abstract translation: 一种在电路中的不同频率输入时钟之间无毛刺切换的技术包括监视每个时钟并确定各个时钟的相对相位何时处于预定的相位差最大值内。 一旦相应时钟的相对相位在可接受的范围内，系统就会从一个时钟切换到另一个时钟。

公开(公告)号：US06781431B2

公开(公告)日：2004-08-24

申请号：US10349033

申请日：2003-01-23

Applicant: Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

Inventor： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

IPC: G06F104

CPC classification number: H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

Abstract: The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

Abstract translation: 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

公开(公告)号：US06779125B1

公开(公告)日：2004-08-17

申请号：US09590596

申请日：2000-06-09

Applicant: Scott Haban

Inventor： Scott Haban

IPC: G06F104

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency. A second frequency multiplier 1304 selectively multiplies the frequency of the third signal by a third factor to obtain a fourth signal of a selected frequency, the second and third factors selected to produce a fourth signal having a frequency of a preselected multiple of a second set of

Abstract translation: 时钟产生电路1300包括用于从所选振荡频率的晶体1301产生第一信号的振荡器1302。 第一倍频器1304选择性地将第一信号的频率乘以预定因子以获得具有第一组时钟信号的预选倍数的频率的第二信号。 分频器1305选择性地将第二信号的频率除以第二因子以获得选定频率的第三信号。 第二倍频器1304选择性地将第三信号的频率乘以第三因子以获得所选频率的第四信号，所选择的第二和第三因素产生第四信号，该第四信号具有第二组的预选倍数

公开(公告)号：US06772361B1

公开(公告)日：2004-08-03

申请号：US09613008

申请日：2000-07-10

Applicant: James J. Walsh

Inventor： James J. Walsh

IPC: G06F104

CPC classification number: G06F21/445 ,  G06F1/14 ,  G06F21/57 ,  G06F21/577 ,  G06F21/6209 ,  G06F2221/2103 ,  G06F2221/2113 ,  G06F2221/2145

Abstract: A real time clock (RTC) is described several timekeeping dependability and timekeeping security attributes. The RTC may have several registers for storing values, at least one of which stores a value which is safeguarded. For example, a “TrustQualityState” register stores a “TrustQualityState” value which is dependent upon a timekeeping accuracy of the RTC. The “TrustQualityState” value may also be dependent upon timekeeping stability, reliability, and/or security of the RTC (e.g., a tamper resistance of the RTC). The RTC includes an access unit coupled between the “TrustQualityState” register and a bus used to access the “TrustQualityState” register. The access unit controls access to the “TrustQualityState” register in order to safeguard the “TrustQualityState” value. The access unit receives read and write commands directed to “TrustQualityState” register via the bus. The access unit determines if a source of a received read or write command directed to the register is authorized to access the register, and provides access to the register only if the source is authorized to access the register. The “TrustQualityState” value may expire a predetermined period of time after issue. In this case, the access unit may also include a counter configured to issue a signal after the predetermined period of time. When the access unit receives the signal from the counter, the access unit may store a default value of “0” in the “TrustQualityState” register.

Abstract translation: 实时时钟（RTC）描述了几个计时可靠性和计时安全属性。 RTC可以具有用于存储值的多个寄存器，其中至少一个存储被保护的值。 例如，“TrustQualityState”寄存器存储“TrustQualityState”值，该值取决于RTC的计时精度。 “TrustQualityState”值也可能取决于RTC的计时稳定性，可靠性和/或安全性（例如RTC的防篡改）。 RTC包括耦合在“TrustQualityState”寄存器和用于访问“TrustQualityState”寄存器的总线之间的访问单元。 访问单元控制对“TrustQualityState”注册器的访问，以保护“TrustQualityState”值。 访问单元通过总线接收指向“TrustQualityState”寄存器的读取和写入命令。 访问单元确定指向寄存器的接收到的读取或写入命令的源是否被授权访问该寄存器，并且只有当源被授权访问该寄存器时才提供对该寄存器的访问。 “TrustQualityState”值可能会在发布后的预定时间段过期。 在这种情况下，访问单元还可以包括配置为在预定时间段之后发出信号的计数器。 当访问单元从计数器接收到信号时，访问单元可以在“TrustQualityState”寄存器中存储默认值“0”。

公开(公告)号：US06768365B2

公开(公告)日：2004-07-27

申请号：US10274191

申请日：2002-10-18

Applicant: Brian W. Curran ,  Edward T. Malley

Inventor： Brian W. Curran ,  Edward T. Malley

IPC: G06F104

CPC classification number: G06F1/32 ,  G06F1/04

Abstract: An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.

Abstract translation: 提供改进的时钟电路用于产生半摆时钟。 以前的电路操作需要额外的电源电压轨（Vdd / 2），但是优选实施例利用电荷共享来产生具有较少功率的半摆动时钟，而不需要额外的电源电压轨。 为了将时钟节点驱动到Vdd / 2，分路晶体管断开，完全充电的时钟节点与完全放电的时钟节点共享其电荷。 当电容正确匹配时，两个节点都将以Vdd / 2的速度进行定位。

公开(公告)号：US06765424B2

公开(公告)日：2004-07-20

申请号：US09989315

申请日：2001-11-20

Applicant: George Zampetti ,  Bob Hamilton

Inventor： George Zampetti ,  Bob Hamilton

IPC: G06F104

CPC classification number: H03L7/07 ,  H04J3/0688

Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract translation: 方法包括接收一对输入时钟信号; 利用层时钟状态机来控制多路复用器; 利用多路复用器在一对输入时钟信号中的每一个之间切换主时钟的输入; 引发相位活动; 并发送输出时钟信号。

公开(公告)号：US06763476B1

公开(公告)日：2004-07-13

申请号：US09825118

申请日：2001-04-03

Applicant: Salil Dangi ,  Roger Andrew Jones

Inventor： Salil Dangi ,  Roger Andrew Jones

IPC: G06F104

CPC classification number: G06F9/4825 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

Abstract: A system and method using a timer management module for managing a circular queue having N Fixed Timer Entries (FTEs) to enable dynamic capacity increase of size M by extending the pointer array referencing the circular queue by M, copying the first “Current Timer Index” entries to the extended pointer array entries, allocating M FTEs, and linking the M FTEs within the circular queue.

Abstract translation: 一种使用定时器管理模块的系统和方法，用于管理具有N个固定定时器条目（FTE）的循环队列，以通过将引用循环队列的指针数组扩展M来实现大小M的动态容量增加，复制第一个“当前定时器索引” 扩展指针数组条目的条目，分配M FTE，以及链接循环队列中的M FTE。