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    Stratum clock state machine multiplexing switching
    1.
    发明授权
    Stratum clock state machine multiplexing switching 失效
    层时钟状态机多路复用切换

    公开(公告)号：US06943609B2

    公开(公告)日：2005-09-13

    申请号：US10782441

    申请日：2004-02-19

    Applicant: George Zampetti ,  Bob Hamilton

    Inventor： George Zampetti ,  Bob Hamilton

    IPC: H03L7/07 ,  H04J3/06 ,  G06F1/04

    CPC classification number: H03L7/07 ,  H04J3/0688

    Abstract: A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

    Abstract translation: 一种方法包括：接收一对输入时钟信号; 利用层时钟状态机来控制多路复用器; 利用多路复用器在一对输入时钟信号中的每一个之间切换主时钟的输入; 引发相位活动; 并发送输出时钟信号。

    Synchronization module
    2.
    发明授权
    Synchronization module 失效
    同步模块

    公开(公告)号：US06876242B2

    公开(公告)日：2005-04-05

    申请号：US10782313

    申请日：2004-02-19

    Applicant: George Zampetti ,  Bob Hamilton

    Inventor： George Zampetti ,  Bob Hamilton

    IPC: H03L7/07 ,  H04J3/06 ,  G06F1/04

    CPC classification number: H03L7/07 ,  H04J3/0688

    Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.

    Abstract translation: 为核心同步模块描述了系统和方法。 一种方法包括：接收一对输入时钟信号; 利用层时钟状态机来控制多路复用器; 利用多路复用器在一对输入时钟信号中的每一个之间切换主时钟的输入; 引发相位活动; 并发送输出时钟信号。 一种装置包括：第一输入时钟数字锁相环; 第二输入时钟数字锁相环; 层时钟状态机耦合到第一输入时钟数字锁相环和第二输入时钟数字锁相环; 以及耦合到第一输入时钟数字锁相环的主时钟锁相环，到第二输入时钟数字锁相和层时钟状态机。

    Stratum clock state machine multiplexer switching
    3.
    发明授权
    Stratum clock state machine multiplexer switching 失效
    层时钟状态机多路复用切换

    公开(公告)号：US06765424B2

    公开(公告)日：2004-07-20

    申请号：US09989315

    申请日：2001-11-20

    Applicant: George Zampetti ,  Bob Hamilton

    Inventor： George Zampetti ,  Bob Hamilton

    IPC: G06F104

    CPC classification number: H03L7/07 ,  H04J3/0688

    Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

    Abstract translation: 方法包括接收一对输入时钟信号; 利用层时钟状态机来控制多路复用器; 利用多路复用器在一对输入时钟信号中的每一个之间切换主时钟的输入; 引发相位活动; 并发送输出时钟信号。

    ENHANCED CLOCK CONTROL IN PACKET NETWORKS
    4.
    发明申请
    ENHANCED CLOCK CONTROL IN PACKET NETWORKS 有权
    分组网络中的增强时钟控制

    公开(公告)号：US20080049743A1

    公开(公告)日：2008-02-28

    申请号：US11669882

    申请日：2007-01-31

    Applicant: George Zampetti

    Inventor： George Zampetti

    IPC: H04L12/56 ,  H04J3/06

    CPC classification number: H04J3/0667 ,  G04G5/00 ,  G06F1/14 ,  H04J3/14 ,  H04L69/28

    Abstract: One embodiment of the present invention sets forth a method for autonomously validating the time and frequency data obtained from multiple sources, and generating a suitable estimate of the frequency difference between the client clock and the source. The method includes the steps of protocol data unit validation, offset measurement, minimum offset filtering, and frequency filtering. With these steps, the negative effects of packet delay variation may be mitigated and a frequency estimate is determined for the source in question, together with an associated validity status. Consequently, quality control of the local clock is achieved in packet networks at significantly reduced cost and decreased level of complexity relative to prior art approaches.

    Abstract translation: 本发明的一个实施例提出了一种用于自主验证从多个源获得的时间和频率数据以及生成客户端时钟和源之间的频率差的适当估计的方法。 该方法包括协议数据单元验证，偏移测量，最小偏移滤波和频率滤波的步骤。 通过这些步骤，可以减轻分组延迟变化的负面影响，并且确定所讨论的源的频率估计以及相关联的有效性状态。 因此，相对于现有技术的方法，在分组网络中实现了本地时钟的质量控制，其显着降低了成本并降低了复杂度。

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