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公开(公告)号：US20240356722A1
公开(公告)日：2024-10-24
申请号：US18761501
申请日：2024-07-02
发明人： Yilong Geng , Deepak Merugu , Balaji S. Prabhakar
摘要： Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines, the coordinator estimates the drift between the pair of machines based on the transit times of probes transmitted between the pair of machines as indicated by the probe records. For different loops of at least three machines in the mesh network, the coordinator calculates a loop drift error based on a sum of the estimated drifts between pairs of machines around the loop and adjusts the estimated absolute drifts of the machines based on the loop drift errors. Here, the absolute drift is defined relative to a drift of a reference machine.
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公开(公告)号：US20240313792A1
公开(公告)日：2024-09-19
申请号：US18185325
申请日：2023-03-16
CPC分类号： H03L7/0992 , H03L1/021 , H03L7/087
摘要： In certain aspects, a system includes a voltage-controlled oscillator (VCO), a phase detector configured to receive a reference signal, a frequency divider coupled between an output of the VCO and the phase detector, a phase-to-current circuit coupled to an output of the phase detector, and a temperature circuit configured to output a temperature-dependent voltage. The system also includes a switching circuit configured to selectively couple the phase-to-current circuit to an input of the VCO and configured to selectively couple the temperature circuit to the input of the VCO.
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公开(公告)号：US12088310B2
公开(公告)日：2024-09-10
申请号：US18192285
申请日：2023-03-29
发明人： Davide Nicolo Fortunato , Antonino Calcagno , Marco Vinciguerra , Angelo Scuderi , Gaetano Cosentino
CPC分类号： H03L7/0992 , H03L7/087 , H03L7/099 , H03L7/103 , H03L7/113 , H03L2207/06
摘要： A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i−1 in the sequence.
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公开(公告)号：US12052021B2
公开(公告)日：2024-07-30
申请号：US17931165
申请日：2022-09-12
CPC分类号： H03L7/0891 , H03L7/087 , H03L7/095
摘要： A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
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公开(公告)号：US11996853B2
公开(公告)日：2024-05-28
申请号：US17196806
申请日：2021-03-09
申请人： INTEL CORPORATION
IPC分类号： H03L7/22 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/14 , H03L7/087 , H03L7/18 , H03L7/23 , H03L7/197 , H03M1/12 , H03M1/50
CPC分类号： H03L7/087 , G06F1/10 , G06F1/12 , G06F1/14 , H03L7/23 , H03L7/235 , H03L7/1976 , H03M1/1255 , H03M1/50
摘要： Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.
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公开(公告)号：US11990914B2
公开(公告)日：2024-05-21
申请号：US17550123
申请日：2021-12-14
摘要： In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
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公开(公告)号：US20240137028A1
公开(公告)日：2024-04-25
申请号：US17992701
申请日：2022-11-22
发明人： Animesh PAUL
CPC分类号： H03L7/087 , H03L7/093 , H03L7/0991
摘要： In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.
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公开(公告)号：US20240088902A1
公开(公告)日：2024-03-14
申请号：US18465898
申请日：2023-09-12
摘要： An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.
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公开(公告)号：US20240063802A1
公开(公告)日：2024-02-22
申请号：US18448946
申请日：2023-08-13
发明人： Siman LI , YOONJOO EOM
摘要： A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.
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公开(公告)号：US20240039543A1
公开(公告)日：2024-02-01
申请号：US18256059
申请日：2020-12-14
CPC分类号： H03L7/095 , H03L7/087 , H03L2207/50
摘要： An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension. The apparatus also comprises a comparator configured to provide the indication of the phase difference based on the digital pulse length representations provided by the first and second TDCs. Corresponding digital phase-locked loop (DPLL) and communication device are also disclosed.
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