公开(公告)号：US20150236550A1

公开(公告)日：2015-08-20

申请号：US13976067

申请日：2011-12-21

申请人： Songnan Yang ,  Emily B. Cooper ,  James J. Walsh ,  Anand S. Konanur

发明人： Songnan Yang ,  Emily B. Cooper ,  James J. Walsh ,  Anand S. Konanur

IPC分类号： H02J17/00 ,  H01Q7/00 ,  H01Q1/22 ,  H01Q1/24

CPC分类号： H02J50/12 ,  H01Q1/2266 ,  H01Q1/243 ,  H01Q7/00 ,  H02J5/005 ,  H02J7/025 ,  H02J50/70 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0081

摘要： Described herein are techniques related to near field coupling (e.g., wireless power transfers (WPF) and near field communications (NFC)) operations among others. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 这里描述了与近场耦合（例如，无线功率传输（WPF）和近场通信（NFC））操作有关的技术。 提交本摘要的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US06708281B1

公开(公告)日：2004-03-16

申请号：US09613009

申请日：2000-07-10

申请人： James J. Walsh

发明人： James J. Walsh

IPC分类号： H04L700

CPC分类号： H04J3/0641

摘要： Several methods for providing an estimate of the current time are described for use in a computer system including a local time source (e.g., a real time clock or RTC). The local time source is capable of holding one of multiple levels of trust with regard to timekeeping, where the levels of trust are ranked with respect to one another. The level of trust of the local time source is dependent upon a timekeeping accuracy of the local time source. The level of trust of the local time source may also be dependent upon a timekeeping stability, a timekeeping reliability, and/or a timekeeping security (e.g., a tamper resistance) of the local time source.

摘要翻译： 描述了用于提供当前时间的估计的几种方法用于包括本地时间源（例如，实时时钟或RTC）的计算机系统。 当地时间来源能够持有关于计时的多个级别的信任，其中信任级别相对于彼此排列。 当地时间来源的信任度取决于当地时间来源的计时精度。 本地时间源的信任级别还可能取决于本地时间源的计时稳定性，计时可靠性和/或计时安全性（例如，抗窜改性）。

公开(公告)号：US5848253A

公开(公告)日：1998-12-08

申请号：US787414

申请日：1997-01-22

申请人： James J. Walsh ,  Joseph Joe ,  Robert W. Milhaupt ,  James Bridgwater ,  Kazumi Haijima

发明人： James J. Walsh ,  Joseph Joe ,  Robert W. Milhaupt ,  James Bridgwater ,  Kazumi Haijima

IPC分类号： G06F13/28 ,  G06F13/14

CPC分类号： G06F13/28 ,  Y02B60/1228

摘要： A computer system (6,7) includes first and second I/O circuits (932, 934), first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (906), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an interface between the notebook computer and the docking station to transfer DMA station. Other devices, systems and methods are also disclosed.

摘要翻译： 计算机系统（6,7）包括分别耦合到第一和第二I / O电路（932,934）的第一和第二I / O电路（932,934），第一和第二总线（904,83），存储器 （106），耦合到存储器（106）的第三总线（104）以及分别连接在第三总线（104）和第一和第二总线（904,83）之间的第一和第二总线接口电路（902,6020） 。 直接存储器访问（DMA）控制器（910）耦合到第一总线（904）和第一总线接口电路（906），串行通信电路（7010,609,10020）连接在DMA控制器 910）和第二总线接口电路（6920）。 作为示例，在本发明中，可以使用单个DMA控制器来使用笔记本计算机和对接站之间的接口来传送DMA站来向笔记本电脑和坞站提供DMA能力。 还公开了其他装置，系统和方法。

公开(公告)号：US5754436A

公开(公告)日：1998-05-19

申请号：US744567

申请日：1996-11-06

申请人： James J. Walsh ,  Jacqueline Brown

发明人： James J. Walsh ,  Jacqueline Brown

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F11/34 ,  G01R19/00

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/30079 ,  G06F11/3423

摘要： A system (100) for computer power management for a computer (102) having a clock (706), includes a plurality of sampling circuits (2360, 2350, 4630, 4720, 4810, 3400, 5300, 5400) responsive to different system activity levels and producing system activity signals representative of the system activity levels. More circuitry (120, 106, 4640) is responsive to the system activity signals and supplies weighted activity output signals adjustably weighting the system activity levels. Filter circuitry (702, 4680) continually responds to the weighted activity output signals to produce a series of duty cycle-related control signals (TONTOFF) representative of directions to pulse-width modulate (MASKCLK) the clock of the computer with such duty cycle. Other devices, systems and methods are also disclosed.

摘要翻译： 一种用于具有时钟（706）的计算机（102）的用于计算机电源管理的系统（100），包括响应于不同系统活动的多个采样电路（2360,2350,4630,4720,4810,3400,5300,5400） 水平并产生代表系统活动水平的系统活动信号。 更多的电路（120,106,4640）对系统活动信号做出响应并提供加权活动输出信号，可调节地对系统活动水平加权。 滤波器电路（702,4680）连续地响应加权的活动输出信号，以产生一系列占空比相关的控制信号（TONTOFF），代表具有这种占空比的计算机的脉冲宽度调制方向（MASKCLK）。 还公开了其他装置，系统和方法。

公开(公告)号：US5734919A

公开(公告)日：1998-03-31

申请号：US705918

申请日：1996-08-29

申请人： James J. Walsh ,  James Bridgwater

发明人： James J. Walsh ,  James Bridgwater

IPC分类号： G06F1/16 ,  G06F1/26 ,  G06F13/00

CPC分类号： G06F1/1632 ,  G06F1/26

摘要： An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5), and a terminal for a selectable supply voltage (VCCDK) and also has a power-good terminal (PWRGOOD5). A plurality of peripheral control circuits (910, 938, 932) are connected by an on-chip internal bus (904). The peripheral control circuits (910, 938, 932) connect to different ones of the internal on-chip supply conductors for operation on the first and second supply voltages (VCC3, VCC5), and the selectable supply voltage (VCCDK). Reset circuitry (2390) is provided for at least one of the peripheral control circuits. A control latch (PMU.sub.-- CNTRL) has a bit (VCCDRV5V) to which the reset circuitry (2390) is responsive. The reset circuitry (2390) provides resets for the at least one of the peripheral control circuits (IDERST, FDDRST) as a function of a voltage at the power-good terminal (PWRGOOD5). Other devices, systems and methods are also disclosed.

公开(公告)号：US5729720A

公开(公告)日：1998-03-17

申请号：US759396

申请日：1996-12-04

申请人： Weiyuen Kau ,  James J. Walsh

发明人： Weiyuen Kau ,  James J. Walsh

IPC分类号： G06F1/16 ,  G06F1/04

CPC分类号： G06F1/04 ,  G06F1/1616 ,  G06F1/1632

摘要： An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU.sub.-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

公开(公告)号：US06564280B1

公开(公告)日：2003-05-13

申请号：US09562401

申请日：2000-05-01

申请人： James J. Walsh

发明人： James J. Walsh

IPC分类号： G06F1300

CPC分类号： G06F13/4031

摘要： A system and method for dynamically configuring communication components in a computer system. The method may operate in a computer system including a plurality of buffers, a plurality of bus master engines and a bus interface unit. A plurality of communication medium interfaces may be coupled to the bus interface unit. Bus master engines, buffers and communication medium interfaces are dynamically configurable so that a set or subset of bus master engine(s), buffer(s) and communication medium interface(s) can be used in either a single or multiple peripheral bus function(s).

摘要翻译： 一种用于在计算机系统中动态配置通信组件的系统和方法。 该方法可以在包括多个缓冲器，多个总线主引擎和总线接口单元的计算机系统中操作。 多个通信介质接口可以耦合到总线接口单元。 总线主引擎，缓冲器和通信介质接口是动态配置的，使得总线主引擎，缓冲器和通信介质接口的集合或子集可以在单个或多个外设总线功能中使用 s）。

公开(公告)号：US5870617A

公开(公告)日：1999-02-09

申请号：US362033

申请日：1994-12-22

申请人： James J. Walsh ,  James Bridgwater

发明人： James J. Walsh ,  James Bridgwater

IPC分类号： G06F1/16 ,  G06F1/26 ,  G06F1/00

CPC分类号： G06F1/1632 ,  G06F1/26

摘要： An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5), and a terminal for a selectable supply voltage (VCCDK) and also has a power-good terminal (PWRGOOD5). A plurality of peripheral control circuits (910, 938, 932) are connected by an on-chip internal bus (904). The peripheral control circuits (910, 938, 932) connect to different ones of the internal on-chip supply conductors for operation on the first and second supply voltages (VCC3, VCC5), and the selectable supply voltage (VCCDK). Reset circuitry (2390) is provided for at least one of the peripheral control circuits. A control latch (PMU.sub.-- CNTRL) has a bit (VCCDRV5V) to which the reset circuitry (2390) is responsive. The reset circuitry (2390) provides resets for the at least one of the peripheral control circuits (IDERST, FDDRST) as a function of a voltage at the power-good terminal (PWRGOOD5). Other devices, systems and methods are also disclosed.

摘要翻译： 集成电路（110）在单个芯片上包括分别连接的不同电源电压端子和内部片上供电导体，包括接地端子（GND）和用于第一和第二电源电压（VCC3，VCC5）的端子，以及 用于可选电源电压的端子（VCCDK），并且还具有电源良好端子（PWRGOOD5）。 多个外围控制电路（910,938,932）通过片上内部总线（904）连接。 外围控制电路（910,938,932）连接到不同的内部片上电源导体，用于在第一和第二电源电压（VCC3，VCC5）和可选电源电压（VCCDK）上操作。 为外围控制电路中的至少一个提供复位电路（2390）。 控制锁存器（PMU-CNTRL）具有复位电路（2390）响应的位（VCCDRV5V）。 复位电路（2390）根据电源良好端子（PWRGOOD5）的电压提供至少一个外围控制电路（IDERST，FDDRST）的复位。 还公开了其他装置，系统和方法。

公开(公告)号：US5842005A

公开(公告)日：1998-11-24

申请号：US854045

申请日：1997-05-08

申请人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

发明人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

IPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/16 ,  G06F1/32 ,  G06F3/00 ,  G06F9/30 ,  G06F1/08

CPC分类号： G06F1/1632 ,  G06F1/10 ,  G06F1/32

摘要： A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

摘要翻译： 微处理器设备（102）包括具有时钟输入的中央处理单元（702），时钟脉冲的时钟发生器（OSC，PLL），具有提供时钟控制信号（SUSP）的输出的逻辑电路（708） 以及由时钟脉冲馈送并且具有耦合到中央处理单元的时钟输入的时钟门输出（CPU-CLK）的时钟门（3610）。 时钟门（3610）响应时钟控制信号（SUSP），以防止所述时钟脉冲（CPU-CLK）在所述时钟控制信号的变化的一个时钟周期内到达中央处理单元。 还公开了其他装置，系统和方法。

公开(公告)号：US5835733A

公开(公告)日：1998-11-10

申请号：US363459

申请日：1994-12-22

申请人： James J. Walsh ,  Joseph Joe ,  Robert W. Milhaupt ,  James Bridgwater ,  Kazumi Haijima

发明人： James J. Walsh ,  Joseph Joe ,  Robert W. Milhaupt ,  James Bridgwater ,  Kazumi Haijima

IPC分类号： G06F13/28 ,  G06F13/14

CPC分类号： G06F13/28 ,  Y02B60/1228

摘要： A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.

摘要翻译： 计算机系统（6,7）包括分别耦合到第一和第二I / O电路（932,934）的第一和第二I / O电路（932,934），51,97第一和第二总线（904,83） ，51,97，存储器（106），耦合到存储器（106）的第三总线（104）以及连接在第三总线（104）与第一和第二总线之间的第一和第二总线接口电路（902,6920） （904,83）。 直接存储器访问（DMA）控制器（910）耦合到第一总线（904）和第一总线接口电路（902），并且串行通信电路（7010,609,10020）连接在DMA控制器 910）和第二总线接口电路（6920）。 作为示例，在本发明中，可以使用单个DMA控制器来使用DMA控制器和对接站中的请求设备之间的相关信息向笔记本电脑和坞站提供DMA能力。 还公开了其他装置，系统和方法。