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    User timer directly programmed by application
    1.
    发明授权
    User timer directly programmed by application 有权

    公开(公告)号：US12099841B2

    公开(公告)日：2024-09-24

    申请号：US17212977

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Rajesh Sankaran ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David Koufaty

    IPC: G06F9/54 ,  G06F9/30 ,  G06F9/48

    CPC classification number: G06F9/30076 ,  G06F9/30101 ,  G06F9/4825

    Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to program a user timer, and execution circuitry to execute the decoded instruction according to the opcode to retrieve timer program information from a location indicated by the first source operand, and program a user timer indicated by the destination operand based on the retrieved timer program information. Other embodiments are disclosed and claimed.

    INTERRUPT MANAGEMENT
    2.
    发明公开
    INTERRUPT MANAGEMENT 审中-公开

    公开(公告)号：US20240311178A1

    公开(公告)日：2024-09-19

    申请号：US18577065

    申请日：2022-07-07

    Applicant: Nordic Semiconductor ASA

    Inventor： Martin Olof OLSSON ,  Frode Milch PEDERSEN

    IPC: G06F9/48 ,  G06F1/28

    CPC classification number: G06F9/4825 ,  G06F1/28

    Abstract: A circuit portion comprises a mapping module, a source component, a destination component and a memory. The mapping module comprises a plurality of channels that each provides a connection for connecting two components of the circuit portion in a one-to-one relationship. The source component is arranged in a first clock or power domain, and the destination component is arranged in a second clock or power domain. In response to an assertion of an event signal or an interrupt by the source component, the mapping module is configured to forward the event signal or interrupt to the destination component via only one channel of the plurality of channels so as to cause the destination component to perform a corresponding task according to a mapping stored in the memory.

    Interrupt coalescing
    5.
    发明授权
    Interrupt coalescing 有权

    公开(公告)号：US10078604B1

    公开(公告)日：2018-09-18

    申请号：US14690349

    申请日：2015-04-17

    Applicant: BiTMICRO Networks, Inc.

    Inventor： Arnaldo Cristobal ,  Marlon Verdan

    IPC: G06F13/24 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/4825

    Abstract: In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.

    SYSTEM AND METHOD FOR PARTITIONING AND MANAGING TIMERS IN A VIRTUALIZED SYSTEM
    7.
    发明申请
    SYSTEM AND METHOD FOR PARTITIONING AND MANAGING TIMERS IN A VIRTUALIZED SYSTEM 审中-公开

    公开(公告)号：US20180165118A1

    公开(公告)日：2018-06-14

    申请号：US15373208

    申请日：2016-12-08

    Applicant: NXP USA, INC.

    Inventor： Ron Michael Bar ,  Eran Glickman ,  Hezi Rahamim

    IPC: G06F9/48 ,  G06F3/06

    CPC classification number: G06F9/4825

    Abstract: A processing system includes a data processor, an input, an output, a memory, an operation parser, and a timer manager instance controller. The input receives create-timer-manager-instance (CTMI) commands identifying a number of timers supported by a timer manager instance. The output provides responses including a CTMI response associated with the CTMI command. The operation parser receives the CTMI command from the input. The timer manager instance controller receive a control input from the operation parser based upon the CTMI command, and in response, allocates a block of memory locations in the memory based on the number of timers and provides a CTMI response to the output to indicate that the CTMI response was executed by the timer manager instance controller.

    System and method for intelligent timer services
    8.
    发明授权
    System and method for intelligent timer services 有权

    公开(公告)号：US09910703B2

    公开(公告)日：2018-03-06

    申请号：US15156480

    申请日：2016-05-17

    Applicant: Accedian Networks Inc.

    Inventor： Andre Dupont ,  Thierry DeCorte

    IPC: G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F1/14

    CPC classification number: G06F9/4881 ,  G06F1/14 ,  G06F9/4825 ,  G06F9/4831 ,  G06F9/4837

    Abstract: A method is provided for efficiently scheduling timer events within an operating system by allocating a plurality of timers, each of which has an expiry time, to a set of available timer slots. The method defines a timer spread value that denotes the allowed variance of the expiry times of each of the timers, calculates a set of available timer slots for each of the timers based on the timer spread value, and adjusts the expiry times of the timers so as to insert and evenly spread the timers across the set of available timer slots. In one implementation, the set of available timer slots is located in a timer wheel existing within the operating system, and the timer wheel uses a plurality of timer vectors arranged into successively increasing levels, beginning with level zero.

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