POLLING SCHEME WITH PRIORITY IN AN INDUSTRIAL NETWORK SYSTEM

    公开(公告)号:US20240232107A9

    公开(公告)日:2024-07-11

    申请号:US18378846

    申请日:2023-10-11

    CPC classification number: G06F13/26 G06F13/225

    Abstract: For polling communication devices in a communication system including a host device and communication devices. The host device is connected to the communication devices via a clock line for transmitting a clock signal to the communication devices and via an arbitration line implemented with “OR” logic for receiving arbitration signal transmitted by the communication devices. Each communication device is configured to pull up or down the arbitration line for sending an arbitration signal when the communication device is ready to send data to the host device. Each communication device is configured to pull down the arbitration line for sending an arbitration signal when the communication device has no data to send to the host device. The host device (HD) is able to: send a clock signal on the clock line during an arbitration cycle, causing the communication devices to send respective arbitration signals towards the arbitration line, during the arbitration cycle, receive a final signal corresponding to an addition of the arbitration signals, during the arbitration cycle, resulting from the “OR” logic applied to the arbitration signals, detect the communication devices ready to send data based on the “1” bit of the final signal, select, among the detected communication devices, the communication device associated with the highest priority in a priority table containing the priorities associated with the communication devices, and poll the selected communication device to receive data from the selected communication device during a communication cycle.

    INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

    公开(公告)号:US20190196993A1

    公开(公告)日:2019-06-27

    申请号:US16206181

    申请日:2018-11-30

    Abstract: An information processing device includes a memory, and a plurality of processor cores capable of accessing the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes, when a polling process for repeatedly determining, by means of polling, whether or not reception data for input/output processing is received is underway in one of the plurality of processor cores, executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.

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