公开(公告)号：US20240248521A1

公开(公告)日：2024-07-25

申请号：US18627428

申请日：2024-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F1/28 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/38 ,  G06F13/26

CPC classification number: G06F1/28 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3887 ,  G06F13/26 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/3016 ,  Y02D10/00

Abstract: In an example, a device includes a memory, a register, a data path including a set of lanes, and a processor that executes a program. The following operations are performed in response to execution of the program: write data to a field of the register, in which the data specifies that at least one lane of the set of lanes is powered on; execute an instruction on the at least one powered on lane; receive an interrupt; based on the interrupt, copy the data from the register to the memory; service the interrupt; and based on completing the service, copy data the data from the memory to the register.

公开(公告)号：US12045182B1

公开(公告)日：2024-07-23

申请号：US18298587

申请日：2023-04-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Christopher Morton ,  Pravesh Gupta ,  Bryan P Broussard ,  Li Ou

IPC: G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F13/26 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/4812 ,  G06F9/4818 ,  G06F9/4831 ,  G06F13/26 ,  G06F13/4221

Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

公开(公告)号：US20240232107A9

公开(公告)日：2024-07-11

申请号：US18378846

申请日：2023-10-11

Applicant: Schneider Electric Industries SAS

Inventor： Bertrand Fruchard ,  Caijin Wang

IPC: G06F13/26 ,  G06F13/22

CPC classification number: G06F13/26 ,  G06F13/225

Abstract: For polling communication devices in a communication system including a host device and communication devices. The host device is connected to the communication devices via a clock line for transmitting a clock signal to the communication devices and via an arbitration line implemented with “OR” logic for receiving arbitration signal transmitted by the communication devices. Each communication device is configured to pull up or down the arbitration line for sending an arbitration signal when the communication device is ready to send data to the host device. Each communication device is configured to pull down the arbitration line for sending an arbitration signal when the communication device has no data to send to the host device. The host device (HD) is able to: send a clock signal on the clock line during an arbitration cycle, causing the communication devices to send respective arbitration signals towards the arbitration line, during the arbitration cycle, receive a final signal corresponding to an addition of the arbitration signals, during the arbitration cycle, resulting from the “OR” logic applied to the arbitration signals, detect the communication devices ready to send data based on the “1” bit of the final signal, select, among the detected communication devices, the communication device associated with the highest priority in a priority table containing the priorities associated with the communication devices, and poll the selected communication device to receive data from the selected communication device during a communication cycle.

公开(公告)号：US11989072B2

公开(公告)日：2024-05-21

申请号：US17838368

申请日：2022-06-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F1/3206 ,  G06F1/28 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/38 ,  G06F13/26

CPC classification number: G06F1/28 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3887 ,  G06F13/26 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/3016 ,  Y02D10/00

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

公开(公告)号：US11782858B2

公开(公告)日：2023-10-10

申请号：US17705298

申请日：2022-03-26

Applicant: AyDeeKay LLC

Inventor： Scott David Kee

IPC: G06F13/36 ,  G06F13/26 ,  G06F13/40 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0866 ,  G06F13/16 ,  G06F13/28 ,  G06F13/364 ,  G06F13/42 ,  G06F13/14 ,  G06F21/76

CPC classification number: G06F13/26 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0638 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/76 ,  G06F2213/0062 ,  G06F2213/40 ,  G06F2221/2103

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

公开(公告)号：US11645217B2

公开(公告)日：2023-05-09

申请号：US17330286

申请日：2021-05-25

Applicant: Western Digital Technologies, Inc.

Inventor： Scott Jinn ,  Yun-Tzuo Lai ,  Haining Liu ,  Yuriy Pavlenko

IPC: G06F13/26 ,  G06F13/374 ,  G06F9/48 ,  G06F9/50 ,  H04W74/00 ,  H04W74/08

CPC classification number: G06F13/374 ,  G06F13/26 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5038 ,  G06F2209/484 ,  H04W74/002 ,  H04W74/0875

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

公开(公告)号：US20190196993A1

公开(公告)日：2019-06-27

申请号：US16206181

申请日：2018-11-30

Applicant: FUJITSU LIMITED

Inventor： Kosuke Suzuki ,  Kohta Nakashima

IPC: G06F13/22 ,  G06F13/26 ,  G06F9/48

CPC classification number: G06F13/225 ,  G06F9/4818 ,  G06F9/4825 ,  G06F9/4881 ,  G06F13/26

Abstract: An information processing device includes a memory, and a plurality of processor cores capable of accessing the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes, when a polling process for repeatedly determining, by means of polling, whether or not reception data for input/output processing is received is underway in one of the plurality of processor cores, executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.

公开(公告)号：US20180329781A1

公开(公告)日：2018-11-15

申请号：US16041267

申请日：2018-07-20

Applicant: EMC IP Holding Company LLC

Inventor： Michael John Dutch ,  Christopher Hercules Claudatos ,  Mandavilli Navneeth Rao

IPC: G06F11/14 ,  G06F13/38 ,  G06F13/26

CPC classification number: G06F11/1448 ,  G06F11/1466 ,  G06F11/1469 ,  G06F13/26 ,  G06F13/385

Abstract: A method, article of manufacture, and apparatus for accessing data during data recovery. In some embodiments, this includes sending an I/O request from an application to an object, wherein the object is being recovered, establishing an I/O intercept, intercepting the application's I/O request with the I/O intercept, and redirecting the I/O request based on the status of the object's sub-objects.

公开(公告)号：US20180314558A1

公开(公告)日：2018-11-01

申请号：US15497481

申请日：2017-04-26

Applicant: Dell Products L.P.

Inventor： Neeraj JOSHI ,  Lucky Pratap KHEMANI

IPC: G06F9/50 ,  G06F13/16 ,  G06F13/26 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/5072 ,  G06F13/1663 ,  G06F13/26 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: In accordance with embodiments of the present disclosure, an information handling system comprising my include a host system comprising a host system processor, and a management controller communicatively coupled to the host system processor and configured to provide management of the information handling system via management traffic communicated between the management controller and a network external to the information handling system and allocate hardware processing resources of the management controller in order to provide compute processing support for the host system processor.

公开(公告)号：US10083134B2

公开(公告)日：2018-09-25

申请号：US14953309

申请日：2015-11-28

Applicant: International Business Machines Corporation

Inventor： Giles R. Frazier ,  Michael Karl Gschwind

IPC: G06F13/32 ,  G06F13/24 ,  G06F9/445 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F9/44505 ,  G06F9/4812 ,  G06F13/26 ,  G06F2209/481

Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.