公开(公告)号：US11281559B2

公开(公告)日：2022-03-22

申请号：US16118498

申请日：2018-08-31

申请人： FUJITSU LIMITED

发明人： Miyuki Matsuo ,  Kohta Nakashima

IPC分类号： G06F11/34 ,  G06F11/30

摘要： An information processing apparatus includes a memory; and a processor coupled to the memory and configured to generate a performance model for calculating a performance value of an application program from a power restriction for each set of parameters of the application program, based on data acquired when a computing apparatus executes the application program for each set of parameters of the application program under each of a plurality of power restrictions; calculate, for each set of parameters of the application program, the performance value of the application program from a first power restriction different from any of the plurality of power restrictions, based on the performance model generated for each set of parameters of the application program; and output a set of parameters of the application program corresponding to a highest performance value of the calculated performance values.

公开(公告)号：US10712794B2

公开(公告)日：2020-07-14

申请号：US15894063

申请日：2018-02-12

申请人： FUJITSU LIMITED

发明人： Miyuki Matsuo ,  Kohta Nakashima

IPC分类号： G06F1/32 ,  G06F1/28

摘要： An apparatus is configured to calculate consumption power of a processor caused by execution of a program, based on sampling data acquired by event-based sampling. The apparatus determines whether the processor is in an idle state, by using the sampling data of a clock event, where the clock event is an event which generates an interrupt at fixed time intervals when the processor is not in the idle state, and which generates the interrupt when a state of the processor changes from the idle state to a non-idle state. In a case where the processor is in the idle state, the apparatus calculates a first amount of consumption power of the processor in the idle state, based on a second amount of consumption power calculated using a consumption power model and a third amount of consumption power included in the sampling data.

公开(公告)号：US10554535B2

公开(公告)日：2020-02-04

申请号：US15608341

申请日：2017-05-30

申请人： FUJITSU LIMITED

发明人： Toshihiro Shimizu ,  Kohta Nakashima

IPC分类号： H04L12/751 ,  H04L12/24 ,  H04L12/725 ,  G06F15/173 ,  H04B10/27 ,  H04B10/40

摘要： An apparatus stores connection information indicating connection relationship among topological structures in a network, in which first-type topological structures are coupled to second-type topological structures. The apparatus stores first transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the first-type topological structures, and second transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the second-type topological structures. The apparatus identifies paths from transmission sources to transmission destinations for a combination of the first and second transfer-patterns, and determines, based on the identified paths, a transfer-pattern with which to perform all-to-all communication without path conflict from the transmission sources to the transmission destinations, and determines output ports in each of the first- and second-type topological structures, corresponding to the identified paths.

公开(公告)号：US10545890B2

公开(公告)日：2020-01-28

申请号：US16206181

申请日：2018-11-30

申请人： FUJITSU LIMITED

发明人： Kosuke Suzuki ,  Kohta Nakashima

IPC分类号： G06F3/00 ,  G06F13/22 ,  G06F13/26 ,  G06F9/48

摘要： An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.

公开(公告)号：US10318362B2

公开(公告)日：2019-06-11

申请号：US15954111

申请日：2018-04-16

申请人： FUJITSU LIMITED

发明人： Yuki Matsuo ,  Munenori Maeda ,  Kohta Nakashima

IPC分类号： G06F9/54

摘要： An information processing apparatus including a memory that stores correspondence information, the correspondence information indicating a correspondence between a plurality of first identifiers and a plurality of combinations of one of a plurality of first threads and one of a plurality of second threads, respectively, and a processor coupled to the memory and the processor configured to execute a process including storing, into a queue, a completion notification corresponding to received data upon a reception of the received data, the received data including a second identifier indicating a combination of transmission source thread among the plurality of second threads and a destination thread among the plurality of first threads, retrieving the completion notification stored in the queue, specifying a third thread among the plurality of first threads based on the second identifier included in the received data and the correspondence information, and transmitting the received data to the third thread.

公开(公告)号：US10178052B2

公开(公告)日：2019-01-08

申请号：US15259113

申请日：2016-09-08

申请人： FUJITSU LIMITED

发明人： Toshihiro Shimizu ,  Kohta Nakashima

IPC分类号： H04B1/69 ,  H04B1/713 ,  H04L12/24 ,  H04L12/931 ,  G06F15/163 ,  H04L12/933

摘要： A parallel information processing apparatus includes a group of switches configured to have a topology of a Latin square, and nodes connected with a switch among the group of switches. The parallel information processing apparatus also include a memory and a processor configured to designate (n×k) units of blocks in the group of switches included in a lattice structure in the topology of the Latin square; to generate information about communication protocol that includes communication directions having different slopes for m (m≤k) units of the nodes, and the number of hops set for the respective communication directions having the different slopes; and to execute communication for the m units of the nodes of the units of the block, based on the information about communication protocol, so as to execute part-to-part communication between the m units of the nodes of the respective units of the blocks.

公开(公告)号：US20180309687A1

公开(公告)日：2018-10-25

申请号：US15954960

申请日：2018-04-17

申请人： FUJITSU LIMITED

发明人： Yuki MATSUO ,  Munenori MAEDA ,  Kohta Nakashima

IPC分类号： H04L12/825 ,  H04L12/861

CPC分类号： H04L47/26 ,  H04L49/90

摘要： An information processing apparatus including a communication interface to communicate with another information processing apparatus, and a processor that executes a process including issuing, by a first thread, a reception request of data from the another information processing apparatus to the communication interface, determining, by using the first thread, whether a completion notification is stored in a queue that stores data transmitted from the other information processing apparatus, causing the first thread to transit to a suspended state when the completion notification is not stored, executing a processing by using a second thread included in the plurality of threads when the first thread is in the suspended state, determining whether the completion notification is stored in the queue after the processing, and transferring the received data to the first thread and causing the first thread to return from the suspended state, upon a storing of the completion notification.

公开(公告)号：US20170085439A1

公开(公告)日：2017-03-23

申请号：US15259113

申请日：2016-09-08

申请人： FUJITSU LIMITED

发明人： Toshihiro Shimizu ,  Kohta Nakashima

IPC分类号： H04L12/24 ,  H04L12/931

CPC分类号： H04L49/351 ,  G06F15/163 ,  H04B1/713 ,  H04L41/083 ,  H04L41/145 ,  H04L49/1507

摘要： A parallel information processing apparatus includes a group of switches configured to have a topology of a Latin square, and nodes connected with a switch among the group of switches. The parallel information processing apparatus also include a memory and a processor configured to designate (n×k) units of blocks in the group of switches included in a lattice structure in the topology of the Latin square; to generate information about communication protocol that includes communication directions having different slopes for m (m≦k) units of the nodes, and the number of hops set for the respective communication directions having the different slopes; and to execute communication for the m units of the nodes of the units of the block, based on the information about communication protocol, so as to execute part-to-part communication between the m units of the nodes of the respective units of the blocks.

公开(公告)号：US09389923B2

公开(公告)日：2016-07-12

申请号：US14066737

申请日：2013-10-30

申请人： FUJITSU LIMITED

发明人： Kohta Nakashima ,  Akira Naruse

IPC分类号： G06F9/45 ,  G06F9/48 ,  G06F9/50

CPC分类号： G06F9/5061 ,  G06F8/458 ,  G06F9/4893 ,  Y02D10/24

摘要： The present invention includes a plurality of computing units executing a plurality of threads including a communication control thread to which a receiving process by polling is assigned. In a CPU core, a computing unit executing the communication control thread performs polling in a memory region indicating notification of arrival of data and waits for execution of the receiving process until arrival of data, and when a computing unit executing an application thread executes a process assigned to the application thread, the computing unit executing the communication control thread moves to a resource-saving mode in which the use of physical resources is suppressed.

摘要翻译： 本发明包括执行多个线程的多个计算单元，所述多个线程包括分配了轮询的接收处理的通信控制线程。 在CPU核心中，执行通信控制线程的计算单元在指示数据到达的通知的存储器区域中执行轮询，并等待数据的到达之前的接收处理的执行，并且当执行应用程序线程的计算单元执行处理 分配给应用程序线程，执行通信控制线程的计算单元移动到抑制物理资源的使用的资源节约模式。

公开(公告)号：US10574478B2

公开(公告)日：2020-02-25

申请号：US16009260

申请日：2018-06-15

申请人： FUJITSU LIMITED

发明人： Toshihiro Shimizu ,  Kohta Nakashima

IPC分类号： H04L12/44 ,  H04L12/24 ,  H04L12/761 ,  H04L12/753 ,  H04L12/707

摘要： An information processing system includes Spine switches, Leaf switches coupled to the Spine switches in a form of a Latin square fat tree, and apparatuses each coupled to any one of the Leaf switches and including a processor. The processor performs, in a case where the processor is included in one of first apparatuses coupled to one of first Leaf switches, first collective communication with others of the first apparatuses on a route via a first Spine switch. The first Leaf switches correspond to at least a portion of points other than points at infinity of a finite projective plane corresponding to the Latin square fat tree. The processor performs second collective communication with others of the first apparatuses on a route via a second Spine switch at each phase of the first collective communication. The second Spine switch is different from the first Spine switch.