知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.018 seconds)

    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
    4.
    发明授权
    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions 有权
    用于动态和静态预测指令资源利用率以生成执行集群分区的多级方案

    公开(公告)号：US07562206B2

    公开(公告)日：2009-07-14

    申请号：US11323043

    申请日：2005-12-30

    Applicant: Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    Inventor： Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    IPC: G06F9/30

    CPC classification number: G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

    Abstract: Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.

    Abstract translation: 公开了用于预测执行群集并促进群集间通信的微架构策略和结构。 在所公开的实施例中，顺序排序的指令被解码成微操作。 预计执行一组微操作涉及执行资源以执行存储器访问操作和集群间通信，但不执行分支操作。 预计第二组微操作的执行涉及执行资源以执行分支操作，但不执行存储器访问操作。 根据这些预测将微操作划分为执行，即第一组执行资源的第一组微操作和第二组执行资源的第二组微操作。 第一组和第二组微操作按顺序执行，并退出以表示其顺序指令排序。

    Determination of cache entry for future operation
    6.
    发明授权
    Determination of cache entry for future operation 有权
    确定高速缓存条目以供将来操作

    公开(公告)号：US07363430B2

    公开(公告)日：2008-04-22

    申请号：US11100273

    申请日：2005-04-06

    Applicant: Samie B. Samaan ,  Avinash Sodani

    Inventor： Samie B. Samaan ,  Avinash Sodani

    IPC: G06F12/12

    CPC classification number: G06F12/123

    Abstract: A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K−1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K−2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K−1)th layer in response to the third hit signal.

    Abstract translation: 系统可以包括M个高速缓存条目，M个高速缓存条目中的每一个用于发送指示从高速缓存条目读取或写入的信号，并且包括数据寄存器和存储器地址寄存器以及K层决策单元，其中K = 日志2 M。 第一层的K层M / 2决定单元指示M个高速缓存条目中相应两个的另一个，并且响应于该信号发送命中信号，第二层M / 4个决定单元， 第一层的M / 2个决定单元中的相应两个中的另一个，并且响应于该信号发送第二命中信号，两个决定单元的第（K-1）层，以使得相应的两个 （K-2）层的决策单元，并且响应于第二命中信号发送第三命中信号，以及根决策单元的第K层，以使得（K-2）层的相应两个决定单元中的另一个能够执行， 1）层响应于第三命中信号。

    Speculatively scheduling micro-operations after allocation
    7.
    发明申请
    Speculatively scheduling micro-operations after allocation 有权
    调配后调度微操作

    公开(公告)号：US20080005535A1

    公开(公告)日：2008-01-03

    申请号：US11479746

    申请日：2006-06-30

    Applicant: Avinash Sodani ,  Rahul Kulkarni ,  David K. Li

    Inventor： Avinash Sodani ,  Rahul Kulkarni ,  David K. Li

    IPC: G06F9/30

    CPC classification number: G06F9/3842 ,  G06F9/384

    Abstract: Apparatus, systems and methods for speculative scheduling of uops after allocation are disclosed including an apparatus having logic to schedule a micro-operation (uop) for execution before source data of the uop is ready. The apparatus further includes logic to cancel dispatching of the uop for execution if the source data is invalid. Other implementations are disclosed.

    Abstract translation: 公开了用于在分配之后的uop的投机调度的装置，系统和方法，包括具有用于在uop的源数据准备就绪之前执行的微操作（uop）的逻辑的装置。 如果源数据无效，该装置还包括用于取消执行uop的调度的逻辑。 公开了其他实现。

    Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures
    8.
    发明授权
    Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures 有权
    用于限制具有高带宽和低带宽结构的寄存器别名表中的端口的方法和装置

    公开(公告)号：US07272701B2

    公开(公告)日：2007-09-18

    申请号：US10692436

    申请日：2003-10-22

    Applicant: Avinash Sodani

    Inventor： Avinash Sodani

    IPC: G06F9/345

    CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/3808 ,  G06F9/384 ,  G06F9/3857

    Abstract: A method and apparatus for a microprocessor with a divided register alias table is disclosed. In one embodiment, a first register alias table may have a full set of read and write ports, and a second register alias table may have a smaller set of read and write ports. The second register alias table may include translations for those logical register addresses that are used less frequently. When the second register alias table is called upon to translate more logical register addresses than it has read ports, in one embodiment a pipeline stall may permit additional time to utilize the limited read ports. In another embodiment, additional build rules for a trace cache may be utilized.

    Abstract translation: 公开了一种具有分割寄存器别名表的微处理器的方法和装置。 在一个实施例中，第一寄存器别名表可以具有完整的读取和写入端口集合，并且第二寄存器别名表可以具有较小的读取和写入端口集合。 第二寄存器别名表可以包括那些频繁使用的逻辑寄存器地址的转换。 当第二寄存器别名表被调用以转换比读取端口更多的逻辑寄存器地址时，在一个实施例中，流水线停顿可以允许额外的时间来利用有限的读取端口。 在另一个实施例中，可以利用跟踪高速缓存的附加构建规则。

    Method and system for memory renaming
    9.
    发明申请
    Method and system for memory renaming 有权
    用于内存重命名的方法和系统

    公开(公告)号：US20050149702A1

    公开(公告)日：2005-07-07

    申请号：US10745700

    申请日：2003-12-29

    Applicant: Sebastien Hily ,  Per Hammarlund ,  Avinash Sodani

    Inventor： Sebastien Hily ,  Per Hammarlund ,  Avinash Sodani

    IPC: G06F9/00 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

    CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3861

    Abstract: Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.

    Abstract translation: 本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。 在一个实施例中，解码单元可以解码加载指令。 如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。 解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。 数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。 如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。 在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

Patent Agency Ranking