公开(公告)号：US20180293073A1

公开(公告)日：2018-10-11

申请号：US15944655

申请日：2018-04-03

申请人： Mohammad A. ABDALLAH

发明人： Mohammad A. ABDALLAH

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06F9/34 ,  G06F9/46

CPC分类号： G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

摘要： A processor architecture includes a register file hierarchy to implement virtual registers that provide a larger set of registers than those directly supported by an instruction set architecture to facilitate multiple copies of the same architecture register for different processing threads, where the register file hierarchy includes a plurality of hierarchy levels. The processor architecture further includes a plurality of execution units coupled to the register file hierarchy.

公开(公告)号：US20180165096A1

公开(公告)日：2018-06-14

申请号：US15374727

申请日：2016-12-09

申请人： Advanced Micro Devices, Inc.

发明人： David N. Suggs

IPC分类号： G06F9/38 ,  G06F12/0875

CPC分类号： G06F9/3808 ,  G06F9/3012 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/6028

摘要： A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.

公开(公告)号：US09892016B2

公开(公告)日：2018-02-13

申请号：US15342698

申请日：2016-11-03

申请人： Dominique Bolignano

发明人： Dominique Bolignano

IPC分类号： G06F9/44 ,  G06F11/36 ,  G06F9/45 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F11/3608 ,  G06F8/443 ,  G06F8/452 ,  G06F8/75 ,  G06F9/30178 ,  G06F9/3808 ,  G06F9/4484 ,  G06F11/362 ,  G06F11/3664

摘要： A method for securing a first program, the first program including a finite number of program points and evolution rules associated to program points and defining the passage of a program point to another, the method including defining a plurality of exit cases and, when a second program is used in the definition of the first program, for each exit case, definition of a branching toward a specific program point of the first program or a declaration of branching impossibility, defining a set of properties to be proven, each associated with one of the constitutive elements of the first program, said set of properties comprising the branching impossibility as a particular property and establishment of the formal proof of the set of properties.

公开(公告)号：US09880846B2

公开(公告)日：2018-01-30

申请号：US13444673

申请日：2012-04-11

申请人： Nathan Tuck ,  Ross Segelken

发明人： Nathan Tuck ,  Ross Segelken

IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/4552

摘要： In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

公开(公告)号：US09804844B2

公开(公告)日：2017-10-31

申请号：US13977728

申请日：2011-09-26

申请人： Elmoustapha Ould-Ahmed-Vall ,  Kshitij A. Doshi ,  Suleyman Sair ,  Charles R. Yount

发明人： Elmoustapha Ould-Ahmed-Vall ,  Kshitij A. Doshi ,  Suleyman Sair ,  Charles R. Yount

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F15/80 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3455 ,  G06F9/3808 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/8061

摘要： Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.

公开(公告)号：US20170277544A1

公开(公告)日：2017-09-28

申请号：US15620837

申请日：2017-06-13

申请人： CENTIPEDE SEMI LTD.

发明人： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC分类号： G06F9/38 ,  G06F11/30

CPC分类号： G06F9/3861 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F11/1402 ,  G06F11/30 ,  G06F11/302 ,  G06F11/3055 ,  G06F11/3065 ,  G06F11/3466

摘要： A processor includes an execution pipeline and monitoring circuity. The execution pipeline is configured to execute instructions of program code. The monitoring circuity is configured to monitor the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions, to parallelize execution of the repetitive sequence based on the corrected specification, and to terminate monitoring of the instructions and discard the specification in response to detecting a branch mis-prediction in the monitored instructions.

公开(公告)号：US09710387B2

公开(公告)日：2017-07-18

申请号：US13359767

申请日：2012-01-27

申请人： Mohammad Abdallah

发明人： Mohammad Abdallah

IPC分类号： G06F12/08 ,  G06F12/0875 ,  G06F9/45 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30174 ,  G06F8/52 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3808 ,  G06F12/0875 ,  G06F2212/151 ,  G06F2212/452

摘要： A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

公开(公告)号：US09632791B2

公开(公告)日：2017-04-25

申请号：US14160242

申请日：2014-01-21

申请人： Apple Inc.

发明人： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/0862

CPC分类号： G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

摘要： Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

公开(公告)号：US09563427B2

公开(公告)日：2017-02-07

申请号：US14291693

申请日：2014-05-30

申请人： International Business Machines Corporation

发明人： Michael K. Gschwind

IPC分类号： G06F9/34 ,  G06F9/42 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44 ,  G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/4486

摘要： Embodiments relate to a system for relative offset branching in a reduced instruction set computing (RISC) architecture. One aspect is a system that includes memory and a processing circuit communicatively coupled to the memory. The system is configured to perform a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A relative offset value is acquired from the instruction stream. The relative offset value is formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width. The relative offset value is added with the program counter value to form a branch target address value. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.

摘要翻译： 实施例涉及在精简指令集计算（RISC）架构中相对偏移分支的系统。 一个方面是包括存储器和通信地耦合到存储器的处理电路的系统。 该系统被配置为执行包括从具有固定指令宽度的指令流获取分支指令的方法。 从指令流获取相对偏移值。 相对偏移值被格式化为相对于程序计数器值的偏移量，并且被设置为固定指令宽度的倍数。 相对偏移值加上程序计数器值，形成分支目标地址值。 分支目标地址值根据分支指令加载到程序计数器中。 基于程序计数器中的分支目标地址值，将指令流的执行重定向到下一条指令。

公开(公告)号：US09507598B1

公开(公告)日：2016-11-29

申请号：US14969492

申请日：2015-12-15

申请人： International Business Machines Corporation

发明人： James J. Bonanno ,  Michael J. Cadigan, Jr. ,  Matthias D. Heizmann ,  Brian R. Prasky

IPC分类号： G06F9/30

CPC分类号： G06F9/30058 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3848 ,  G06F9/3861

摘要： According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

摘要翻译： 根据一方面，提供了在包括主分支预测器和辅助分支预测器的处理系统中辅助分支预测的管理。 基于接收到与主分支预测器的错误预测目标地址相对应的主分支预测器误预测指标来定位辅助分支预测器的同余类。 在一致类中标识一个条目，其中辅助有用性级别相对于一致性类别的一个或多个其他条目设置为最低有用级别。 与错误的目标地址相对应的辅助数据安装在条目中。 根据安装辅助数据，将条目的辅助功能级别重置为初始值。