公开(公告)号：US20240134572A1

公开(公告)日：2024-04-25

申请号：US18401558

申请日：2023-12-31

Applicant: Imagination Technologies Limited

Inventor： Isuru Herath ,  Richard Broadhurst

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/50

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/30101 ,  G06F9/324 ,  G06F9/5016

Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

公开(公告)号：US11727257B2

公开(公告)日：2023-08-15

申请号：US17582904

申请日：2022-01-24

Applicant: Cerebras Systems Inc.

Inventor： Sean Lie ,  Michael Morrison ,  Srikanth Arekapudi ,  Gary R. Lauterbach ,  Michael Edwin James

IPC: G06F13/10 ,  G06N3/063 ,  G06F9/30 ,  G06F17/16 ,  G06F9/455 ,  G06N3/08 ,  G06F13/00 ,  G06F9/32 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06N3/04 ,  G06F15/82 ,  G06N3/045 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06F9/3005 ,  G06F9/3016 ,  G06F9/30036 ,  G06F9/30192 ,  G06F9/324 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/00 ,  G06F15/825 ,  G06F17/16 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Instructions executed by the compute element include operand specifiers, some specifying a data structure register storing a data structure descriptor describing an operand as a fabric vector or a memory vector. The data structure descriptor further describes the memory vector as one of a one-dimensional vector, a four-dimensional vector, or a circular buffer vector. Optionally, the data structure descriptor specifies an extended data structure register storing an extended data structure descriptor. The extended data structure descriptor specifies parameters relating to a four-dimensional vector or a circular buffer vector.

公开(公告)号：US20180113784A1

公开(公告)日：2018-04-26

申请号：US15841814

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind

IPC: G06F11/36 ,  G06F9/38

CPC classification number: G06F11/362 ,  G06F9/3017 ,  G06F9/324 ,  G06F9/38

Abstract: A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap.

公开(公告)号：US09940262B2

公开(公告)日：2018-04-10

申请号：US14491149

申请日：2014-09-19

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC: G06F12/1045 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/1027

CPC classification number: G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

公开(公告)号：US20160085550A1

公开(公告)日：2016-03-24

申请号：US14491149

申请日：2014-09-19

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

Abstract translation: 一种有效指示分支目标地址的系统和方法。 在将指令安装到指令高速缓存之前，半导体芯片预先对计算机程序的指令进行解码。 响应于确定特定指令是具有相对于程序计数器地址（PC）的位移的控制流程指令，芯片用目标地址的子集替换特定指令中的PC相对位移的一部分。 目标地址的子集是完整目标地址的非翻译物理子集。 当重新编码的特定指令被取出和解码时，PC相对位移的剩余部分被添加到用于获取特定指令的PC的虚拟部分。 结果与嵌入在获取的特定指令中的目标地址的部分连接以形成完整的目标地址。

公开(公告)号：US09250904B2

公开(公告)日：2016-02-02

申请号：US14139895

申请日：2013-12-24

Applicant: International Business Machines Corporation

Inventor： Michael K Gschwind ,  Eric M Schwarz

IPC: G06F9/00 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/342

Abstract: An modify next sequential instruction (MNSI) instruction, when executed, modifies a field of the fetched copy of the next sequential instruction (NSI) to enable a program to dynamically provide parameters to the NSI being executed. Thus the MNSI instruction is a non-disruptive prefix instruction to the NSI. The NSI may be modified to effectively extend the length of the NSI field, thus providing more registers or more range (in the case of a length field) than otherwise available to the NSI instruction according to the instruction set architecture (ISA).

Abstract translation: 修改下一个顺序指令（MNSI）指令，当执行时，修改下一个顺序指令（NSI）的获取副本的一个字段，以使程序能够动态地向被执行的NSI提供参数。 因此，MNSI指令是NSI的非中断前缀指令。 可以修改NSI以有效地扩展NSI字段的长度，从而根据指令集体系结构（ISA）提供更多的寄存器或更多的范围（在长度字段的情况下）比NSI指令可用的更多的范围。

公开(公告)号：US20150347146A1

公开(公告)日：2015-12-03

申请号：US14291693

申请日：2014-05-30

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/4486

Abstract: Embodiments relate to a system for relative offset branching in a reduced instruction set computing (RISC) architecture. One aspect is a system that includes memory and a processing circuit communicatively coupled to the memory. The system is configured to perform a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A relative offset value is acquired from the instruction stream. The relative offset value is formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width. The relative offset value is added with the program counter value to form a branch target address value. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.

Abstract translation: 实施例涉及在精简指令集计算（RISC）架构中相对偏移分支的系统。 一个方面是包括存储器和通信地耦合到存储器的处理电路的系统。 该系统被配置为执行包括从具有固定指令宽度的指令流获取分支指令的方法。 从指令流获取相对偏移值。 相对偏移值被格式化为相对于程序计数器值的偏移量，并且被设置为固定指令宽度的倍数。 相对偏移值加上程序计数器值，形成分支目标地址值。 分支目标地址值根据分支指令加载到程序计数器中。 基于程序计数器中的分支目标地址值，将指令流的执行重定向到下一条指令。

公开(公告)号：US20150324199A1

公开(公告)日：2015-11-12

申请号：US14410127

申请日：2013-07-06

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Mina DENG ,  Paulus Mathias Hubertus Mechtildis Antonius GORISSEN ,  Ludovicus Marinus Gerardus Maria TOLHUIZEN ,  Arnoldus Jeroen NIESSEN

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F1/03 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30061 ,  G06F9/324 ,  G06F9/3867

Abstract: A computer system comprising a processor and a memory, the processor comprising an instruction cycle circuit configured to repeatedly obtain a next instruction of a computer program, an instruction decoder configured to decode and execute the instruction obtained by the instruction cycle circuit, the computer system supporting multiple arithmetic and/or logic operations under control of one or more of the instructions, wherein the memory stores multiple tables, each specific one of the multiple arithmetic and/or logic operations being supported by a specific table stored in the memory, each specific table comprising the result of the specific arithmetic operations for a range of inputs.

Abstract translation: 一种包括处理器和存储器的计算机系统，所述处理器包括指令周期电路，其被配置为重复获得计算机程序的下一指令，指令解码器，被配置为解码并执行由所述指令周期电路获得的指令，所述计算机系统支持 在一个或多个指令的控制下的多个算术和/或逻辑操作，其中存储器存储多个表，多个算术和/或逻辑运算中的每个特定的一个由存储在存储器中的特定表支持，每个特定表 包括一系列输入的具体算术运算结果。

公开(公告)号：US08966228B2

公开(公告)日：2015-02-24

申请号：US12382690

申请日：2009-03-20

Applicant: Simon John Craske ,  Chiloda Ashan Senerath Pathirane

Inventor： Simon John Craske ,  Chiloda Ashan Senerath Pathirane

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/32

CPC classification number: G06F9/321 ,  G06F9/324

Abstract: This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount.

Abstract translation: 该应用涉及用于从数据存储器取出指令以供数据处理器处理的设备和方法。 该装置包括：用于存储由所述数据处理器处理的指令的地址的寄存器; 提取单元，响应于输入到所述提取单元的地址以获取存储在所述地址处的指令; 一个加法器，用于在将所述地址发送到所述提取单元之前，将存储在所述寄存器中的所述地址相加预定量，所述预定量确定所述取得的指令中的位置相对于在所述寄存器中寻址的所述指令; 所述加法器响应于检测到程序流程的改变以将所述预定量重置为初始值，并且为了后续提取增加所述预定量以等于地址之间的间隔，使得连续地址被提取到最大值 预定量。

公开(公告)号：US20140164741A1

公开(公告)日：2014-06-12

申请号：US14139895

申请日：2013-12-24

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind ,  Eric M. Schwarz

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/324 ,  G06F9/342

Abstract: An modify next sequential instruction (MNSI) instruction, when executed, modifies a field of the fetched copy of the next sequential instruction (NSI) to enable a program to dynamically provide parameters to the NSI being executed. Thus the MNSI instruction is a non-disruptive prefix instruction to the NSI. The NSI may be modified to effectively extend the length of the NSI field, thus providing more registers or more range (in the case of a length field) than otherwise available to the NSI instruction according to the instruction set architecture (ISA)

Abstract translation: 修改下一个顺序指令（MNSI）指令，当执行时，修改下一个顺序指令（NSI）的获取副本的一个字段，以使程序能够动态地向被执行的NSI提供参数。 因此，MNSI指令是NSI的非中断前缀指令。 可以修改NSI以有效地扩展NSI字段的长度，从而根据指令集架构（ISA）提供更多的寄存器或更多的范围（在长度字段的情况下）比NSI指令可用的更多的范围