公开(公告)号：US20130275684A1

公开(公告)日：2013-10-17

申请号：US13444673

申请日：2012-04-11

Applicant: Nathan Tuck ,  Ross Segelken

Inventor： Nathan Tuck ,  Ross Segelken

IPC: G06F12/08

CPC classification number: G06F9/3808 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/4552

Abstract: In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

Abstract translation: 在一个实施例中，微处理系统包括设置在处理器核心上的硬件结构。 硬件结构包括多个条目，每个条目与代码的一部分相关联，并且该代码的转换可以被执行以实现基本相同的功能。 硬件结构包括重定向阵列，当被引用时，执行被重定向到一部分代码到其对应的转换。 基于条目的使用信息，启用这种重定向的条目被保持在硬件结构内或从硬件结构中驱逐。

公开(公告)号：US20070255894A1

公开(公告)日：2007-11-01

申请号：US11352192

申请日：2006-02-10

Applicant: Richard Hessel ,  Nathan Tuck ,  Korbin Van Dyke ,  Chetana Keltcher

Inventor： Richard Hessel ,  Nathan Tuck ,  Korbin Van Dyke ,  Chetana Keltcher

IPC: G06F13/28

CPC classification number: G11C7/1072 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8061

Abstract: A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.

Abstract translation: 矢量处理系统使用片上系统（SOC）实现技术提供高性能矢量处理。 一个或多个标量处理器（或核）与矢量处理器一起操作，并且处理器共同共享对耦合到动态随机存取读/写存储器（DRAM）的多个存储器接口的访问。 在典型实施例中，向量处理器作为标量处理器的从属单元操作，响应于从标量处理器接收的命令执行计算密集型单指令多数据（SIMD）代码。 向量处理器实现包括机器状态，指令集，异常模型和存储器模型的向量处理指令集体系结构（ISA）。

公开(公告)号：US20070165035A1

公开(公告)日：2007-07-19

申请号：US11613093

申请日：2006-12-19

Applicant: Jerome Duluk ,  Richard Hessel ,  Vaughn Arnold ,  Jack Benkual ,  Joseph Bratt ,  George Cuan ,  Stephen Dodgen ,  Emerson Fang ,  Zhaoyu Gong ,  Thomas Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew Papakipos ,  Jason Redgrave ,  Sushma Trivedi ,  Nathan Tuck ,  Shun Go ,  Lindy Fung ,  Tuan Nguyen ,  Joseph Grass ,  Bo Hung ,  Abraham Mammen ,  Abbas Rashid ,  Albert Tsay

Inventor： Jerome Duluk ,  Richard Hessel ,  Vaughn Arnold ,  Jack Benkual ,  Joseph Bratt ,  George Cuan ,  Stephen Dodgen ,  Emerson Fang ,  Zhaoyu Gong ,  Thomas Ho ,  Hengwei Hsu ,  Sidong Li ,  Sam Ng ,  Matthew Papakipos ,  Jason Redgrave ,  Sushma Trivedi ,  Nathan Tuck ,  Shun Go ,  Lindy Fung ,  Tuan Nguyen ,  Joseph Grass ,  Bo Hung ,  Abraham Mammen ,  Abbas Rashid ,  Albert Tsay

IPC: G06T1/20

CPC classification number: G06T15/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/30 ,  G06T15/40 ,  G06T15/50 ,  G06T15/80 ,  G06T15/83 ,  G06T15/87

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract translation: 提供了包括许多子结构的延迟着色图形流水线处理器和方法。 处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。 在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。 流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元， 像素单元和后端单元。

公开(公告)号：US09880846B2

公开(公告)日：2018-01-30

申请号：US13444673

申请日：2012-04-11

Applicant: Nathan Tuck ,  Ross Segelken

Inventor： Nathan Tuck ,  Ross Segelken

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3808 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/4552

Abstract: In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

公开(公告)号：US20140052962A1

公开(公告)日：2014-02-20

申请号：US13586700

申请日：2012-08-15

Applicant: Ben Hertzberg ,  Nathan Tuck

Inventor： Ben Hertzberg ,  Nathan Tuck

IPC: G06F9/30

CPC classification number: G06F9/30174 ,  G06F9/322 ,  G06F9/3808

Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.

Abstract translation: 处理系统包括微处理器，布置在微处理器内的硬件解码器以及可操作地耦合到微处理器的转换器。 硬件解码器被配置为对微处理器非本机的指令代码进行解码以在微处理器中执行。 翻译器被配置为在微处理器本机的指令集中形成指令代码的翻译，并将转换中的分支指令连接到链接存根。 链接存根被配置为选择性地使得在分支指令的目标地址处的附加指令代码被接收在硬件解码器中，而不使处理系统搜索目标地址处的附加指令代码的转换。

公开(公告)号：US06771264B1

公开(公告)日：2004-08-03

申请号：US09213990

申请日：1999-12-17

Applicant: Jerome F. Duluk ,  Stephen L. Dodgen ,  Joseph P. Bratt ,  Matthew Papakipos ,  Nathan Tuck ,  Richard E. Hessel

Inventor： Jerome F. Duluk ,  Stephen L. Dodgen ,  Joseph P. Bratt ,  Matthew Papakipos ,  Nathan Tuck ,  Richard E. Hessel

IPC: G06T1560

CPC classification number: G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/20 ,  G06T15/405 ,  G06T15/50 ,  G06T15/83

Abstract: A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (vs, vt, n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor. The Phong shader performs all lighting computations in eye space, which requires it first to transform bump data from tangent space to eye space. In one embodiment the Phong hardware does this by multiplying a matrix M whose columns comprise eye space basis vectors (bs, bt, n) derived from the surface basis vectors (vs, vt, n) and the vector Tb of bump map data. The eye space basis vectors are derived by the DSGP preprocessor so that the multiplication (M×Tb) gives the perturbed surface normal N′ in eye space, reflecting the bump effects. The perturbed surface normal N′ is subsequently used in the lighting computations.

Abstract translation: 用于在延迟着色图形处理器（DSGP）中执行切线空间照明的系统和方法包括预处理数据的DSGP的块和仅在所有片段被预处理之后才执行的Phong着色器。 预处理器块接收以各种格式指定的纹理贴图，并将这些纹理贴图转换为普通格式供Phong着色器使用。 预处理器块为Phong着色器提供了内插表面基向量（vs，vt，n），一个向量Tb，它在切向/对象空间中表示纹理贴图中的纹理/凹凸数据，光数据，材料数据，眼睛坐标等 Phong着色器使用的信息执行照明和凹凸贴图计算。 为需要计算照明效果的每个片段提供来自预处理器的数据。 Phong着色器使用预处理器提供的信息计算片段的颜色。 Phong着色器执行眼睛空间中的所有照明计算，这需要它首先将凹凸数据从切线空间转换为眼睛空间。 在一个实施例中，Phong硬件通过乘以其列包括从表面基矢量（vs，vt，n）导出的凹凸贴图数据的矢量Tb的基准矢量（bs，bt，n）的矩阵M来实现。 通过DSGP预处理器导出眼空间基矢量，使得乘法（MxTb）给出了眼空间中的扰动表面法线N'，反映了碰撞效应。 扰动表面法线N'随后用于照明计算。

公开(公告)号：US10146545B2

公开(公告)日：2018-12-04

申请号：US13419323

申请日：2012-03-13

Applicant: Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

Inventor： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/1018 ,  G06F12/0862 ,  G06F9/38

Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

公开(公告)号：US09384001B2

公开(公告)日：2016-07-05

申请号：US13586700

申请日：2012-08-15

Applicant: Ben Hertzberg ,  Nathan Tuck

Inventor： Ben Hertzberg ,  Nathan Tuck

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/40 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/322 ,  G06F9/3808

Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.

Abstract translation: 处理系统包括微处理器，布置在微处理器内的硬件解码器以及可操作地耦合到微处理器的转换器。 硬件解码器被配置为对微处理器非本机的指令代码进行解码以在微处理器中执行。 翻译器被配置为在微处理器本机的指令集中形成指令代码的翻译，并将转换中的分支指令连接到链接存根。 链接存根被配置为选择性地使得在分支指令的目标地址处的附加指令代码被接收在硬件解码器中，而不使处理系统搜索目标地址处的附加指令代码的转换。

公开(公告)号：US20130246709A1

公开(公告)日：2013-09-19

申请号：US13419323

申请日：2012-03-13

Applicant: Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

Inventor： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

IPC: G06F12/08

CPC classification number: G06F9/30181 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3802 ,  G06F12/0862 ,  G06F12/1018

Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

Abstract translation: 提供了与从微处理器中包括的指令高速缓存的指令获取相同功能的取指令和替代版本的实施例。 在一个示例中，提供了一种方法，其包括以示例性微处理器从指令高速缓存取出指令。 示例性方法还包括对用于指令的地址进行散列以确定实现与指令相同功能的指令的替代版本是否存在。 该示例方法还包括，如果散列导致存在这样的替代版本的确定，则中止提取指令并检索和执行备用版本。