Invention Application
- Patent Title: TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR
- Patent Title (中): 微处理器的翻译地址缓存
-
Application No.: US13419323Application Date: 2012-03-13
-
Publication No.: US20130246709A1Publication Date: 2013-09-19
- Inventor: Ross Segelken , Alex Klaiber , Nathan Tuck , David Dunn
- Applicant: Ross Segelken , Alex Klaiber , Nathan Tuck , David Dunn
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.
Public/Granted literature
- US10146545B2 Translation address cache for a microprocessor Public/Granted day:2018-12-04
Information query