Abstract:
An integrated testing device and method are disclosed. The device includes an integral reservoir for a test fluid, and an actuator, so that the test fluid can be dispensed to facilitate the test.
Abstract:
An integrated testing device and method are disclosed. The device includes an integral reservoir for a test fluid, and an actuator, so that the test fluid can be dispensed to facilitate the test.
Abstract:
A method, an x86 processor and a computer system for processing more securely. More specifically, embodiments provide an effective and efficient mechanism for reducing APIC interference with accesses to SMRAM, where processor modifications implementing this mechanism effectively reduce APIC attacks and increase the security of proprietary, confidential or otherwise secure data stored in SMRAM.
Abstract:
A composite diagnostic system comprising a support member having a membrane penetration element; a bodily fluid collection point positioned for collection of a bodily fluid released by application of the membrane penetration element to a user's body; a test material positioned in the support member such that in use the bodily fluid is brought into contact with the test material.
Abstract:
An two-piece, corner framing element is described for connecting two longitudinal swimming pool extrusions having longitudinal pool-liner channels that utilizes the conventional upward projecting liner-anchoring land along a bottom front edge of the pool-liner channels for angularly orienting and securing the longitudinal extrusions together in the field framing a pool corner wall during construction of a swimming pool.
Abstract:
A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
Abstract:
An two-piece, corner framing element is described for connecting two longitudinal swimming pool extrusions having longitudinal pool-liner channels that utilizes the conventional upward projecting liner-anchoring land along a bottom front edge of the pool-liner channels for angularly orienting and securing the longitudinal extrusions together in the field for framing a corner structure for pool walls as a pool is being constructed.
Abstract:
A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
Abstract:
Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocessor, while speculation normally permitted for certain other operations is suspended. Accordingly, while the fault is dispatched, some speculation is permitted as opposed to suspending all speculation. As such, microcode that makes use of speculation can be written.
Abstract:
Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.