公开(公告)号：US09652244B2

公开(公告)日：2017-05-16

申请号：US13532517

申请日：2012-06-25

Applicant: Alexander Klaiber ,  Guillermo Rozas

Inventor： Alexander Klaiber ,  Guillermo Rozas

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/30134 ,  G06F9/3826 ,  G06F9/384

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

公开(公告)号：US08656214B2

公开(公告)日：2014-02-18

申请号：US12786339

申请日：2010-05-24

Applicant: Guillermo Rozas ,  Alex Klaiber ,  Robert Masleid

Inventor： Guillermo Rozas ,  Alex Klaiber ,  Robert Masleid

IPC: G06F11/00 ,  G11C29/00

CPC classification number: G06F11/1666 ,  G06F11/1064 ,  G06F11/20 ,  G06F12/0853

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract translation: 双端口复制数据高速缓存。 高速缓存配置为存储输入数据块。 高速缓存包括用于产生具有来自输入数据块的奇偶校验信息的增强数据块的增强器，用于存储增强数据块的第一存储器阵列和用于存储增强数据块的第二存储器阵列。

公开(公告)号：US08209518B2

公开(公告)日：2012-06-26

申请号：US13073895

申请日：2011-03-28

Applicant: Alexander Klaiber ,  Guillermo Rozas

Inventor： Alexander Klaiber ,  Guillermo Rozas

IPC: G06F9/34

CPC classification number: G06F9/3838 ,  G06F9/30134 ,  G06F9/3826 ,  G06F9/384

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract translation: 公开了一种处理旁路目录系统和方法。 在一个实施例中，旁路目录跟踪处理包括在写入对应的体系结构寄存器时在旁路目录中设置位。 每个周期在旁路目录中选择性地清零这些位。 利用这些位的配置来确定旁路路径处理信息的哪个阶段。

公开(公告)号：US20110179256A1

公开(公告)日：2011-07-21

申请号：US13073895

申请日：2011-03-28

Applicant: Alexander Klaiber ,  Guillermo Rozas

Inventor： Alexander Klaiber ,  Guillermo Rozas

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/30134 ,  G06F9/3826 ,  G06F9/384

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract translation: 公开了一种处理旁路目录系统和方法。 在一个实施例中，旁路目录跟踪处理包括在写入对应的体系结构寄存器时在旁路目录中设置位。 每个周期在旁路目录中选择性地清零这些位。 利用这些位的配置来确定旁路路径处理信息的哪个阶段。

公开(公告)号：US07873793B1

公开(公告)日：2011-01-18

申请号：US11807629

申请日：2007-05-29

Applicant: Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

Inventor： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/603

Abstract: Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.

Abstract translation: 提供和描述了用于支持数据高速缓存中的推测性修改的方法和系统。 数据高速缓存包括多条高速缓存行。 每个高速缓存线包括用于指示多个状态中的任何一个的状态指示符，其中，所述多个状态包括能够跟踪对相应高速缓存线中的数据的推测性修改的推测状态。 响应于在推测性执行指令期间到达特定指令边界时执行的第一操作，推测状态使得对相应高速缓存行中的数据进行推测性修改是永久性的。 此外，推测状态使得能够响应于在推测性执行指令期间不能达到特定指令边界时执行的第二操作来撤消对相应高速缓存行中的数据的推测性修改。

公开(公告)号：US07634635B1

公开(公告)日：2009-12-15

申请号：US11400631

申请日：2006-04-07

Applicant: Brian Holscher ,  Guillermo Rozas ,  James Van Zoeren ,  David Dunn

Inventor： Brian Holscher ,  Guillermo Rozas ,  James Van Zoeren ,  David Dunn

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3865

Abstract: Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension, wherein the instruction extension is transparent to the programming model of the microprocessor. The instruction extension may comprise a field for indicating an offset from a memory structure pointer. The microprocessor includes circuitry for adding the offset to the memory structure pointer to indicate a specific element of the memory structure. The specific element of the memory structure comprises address information corresponding to speculative data.

Abstract translation: 用于重新排序处理器指令的系统和方法。 根据本发明的第一实施例，微处理器包括处理指令扩展的电路，其中指令扩展对于微处理器的编程模型是透明的。 指令扩展可以包括用于指示来自存储器结构指针的偏移的字段。 微处理器包括用于将偏移量添加到存储器结构指针以指示存储器结构的特定元件的电路。 存储器结构的特定元件包括对应于推测数据的地址信息。

公开(公告)号：US20070233961A1

公开(公告)日：2007-10-04

申请号：US11395627

申请日：2006-03-31

Applicant: John Banning ,  Guillermo Rozas

Inventor： John Banning ,  Guillermo Rozas

IPC: G06F12/00

CPC classification number: G06F12/0846 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3885 ,  G06F12/0875 ,  G06F12/0886

Abstract: An instruction memory for storing a plurality of instruction bits. A first portion of the instruction memory is for storing a first subset of bits of the plurality of instruction bits. A second portion of the instruction memory is for storing a second subset of bits of the plurality of instruction bits, wherein the second subset of bits is operable to be accessed by an instruction extractor during an instruction extraction earlier than the first subset of bits.

Abstract translation: 一种用于存储多个指令位的指令存储器。 指令存储器的第一部分用于存储多个指令位的位的第一子集。 指令存储器的第二部分用于存储多个指令位的位的第二子集，其中第二比特子集可操作以在指令提取器之前在比第一比特的子集更早的指令提取期间被访问。

公开(公告)号：US07149851B1

公开(公告)日：2006-12-12

申请号：US10646461

申请日：2003-08-21

Applicant: Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

Inventor： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC: G06F12/16

CPC classification number: G06F12/0855 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857

Abstract: Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.

公开(公告)号：US06725361B1

公开(公告)日：2004-04-20

申请号：US09595199

申请日：2000-06-16

Applicant: Guillermo Rozas ,  David Dunn ,  David Dobrikin ,  Alex Klaiber ,  Daniel H. Nelsen

Inventor： Guillermo Rozas ,  David Dunn ,  David Dobrikin ,  Alex Klaiber ,  Daniel H. Nelsen

IPC: G06F1500

CPC classification number: G06F9/30134 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/384

Abstract: A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.

Abstract translation: 一种浮点处理器，包括多个可明确寻址的处理器寄存器，能够存储用于逻辑地重命名可明确寻址的寄存器以仿真浮点堆栈的寄存器的值的仿真寄存器，用于计算和改变的计算机可执行软件过程 仿真寄存器中的值到执行浮点堆栈操作时指示浮点堆栈寄存器的地址变化的值，以及加法器电路，其响应于计算机可执行程序组合寄存器地址和仿真寄存器中的值 处理以重命名多个可明确寻址的处理器寄存器。

公开(公告)号：US06205466B1

公开(公告)日：2001-03-20

申请号：US09118248

申请日：1998-07-17

Applicant: Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Ernest Mak ,  Sandeep Kumar ,  Guillermo Rozas ,  Chia-Chiang Chao ,  Venkatesh Krishnan ,  Alexandre Bronstein

Inventor： Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Ernest Mak ,  Sandeep Kumar ,  Guillermo Rozas ,  Chia-Chiang Chao ,  Venkatesh Krishnan ,  Alexandre Bronstein

IPC: G06F900

CPC classification number: G06F9/468 ,  G06F21/6218 ,  G06F21/6236 ,  G06F2221/2141 ,  G06Q10/10 ,  Y10S707/99931 ,  Y10S707/99932

Abstract: A software infrastructure for providing an open digital services marketplace including a naming manager that enables a requesting task to refer to a desired resource using a name which is local to the requesting task and a router that forwards the request to an appropriate handler for the desired resource and that enables at least one additional task to be invoked in response to the request. The infrastructure includes a permission manager that compares a set of access rights of the requesting task to the desired resource to a set of permissions associated with the desired resource such that the access rights are kept separately from the reference to the desired resource. The desired resource, the requesting task, the additional task, and a set of additional components used to handle the request are each modeled as a resource defined by a corresponding set of meta-data which includes a set of attributes and a reference to a grammar for interpreting the attributes.

Abstract translation: 一种用于提供开放数字服务市场的软件基础设施，包括命名管理器，其允许请求任务使用请求任务本地的名称引用期望的资源，以及将请求转发到所需资源的适当处理程序的路由器 并且这使得能够响应于该请求调用至少一个附加任务。 基础设施包括权限管理器，其将请求任务的一组访问权限与期望的资源进行比较，以与所需资源相关联的一组权限进行比较，使得访问权限与对期望的资源的引用分开地保持。 所需资源，请求任务，附加任务和用于处理请求的一组附加组件各自被建模为由对应的一组元数据定义的资源，该元数据包括一组属性和对语法的引用 用于解释属性。