公开(公告)号：US20140082291A1

公开(公告)日：2014-03-20

申请号：US13620070

申请日：2012-09-14

申请人： James Van Zoeren ,  Alexander Klaiber ,  Guillermo J. Rozas ,  Paul Serris

发明人： James Van Zoeren ,  Alexander Klaiber ,  Guillermo J. Rozas ,  Paul Serris

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/1024

摘要： In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.

摘要翻译： 在处理器中，用于访问共享存储器的投机许可获取的方法。 该方法包括从处理器核心接收存储以修改共享高速缓存行，以及响应于接收到存储，将高速缓存行标记为推测。 然后根据商店修改缓存行。 接收到修改许可后，修改的高速缓存行随后被提交。

公开(公告)号：US07873793B1

公开(公告)日：2011-01-18

申请号：US11807629

申请日：2007-05-29

申请人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

发明人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/603

摘要： Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.

摘要翻译： 提供和描述了用于支持数据高速缓存中的推测性修改的方法和系统。 数据高速缓存包括多条高速缓存行。 每个高速缓存线包括用于指示多个状态中的任何一个的状态指示符，其中，所述多个状态包括能够跟踪对相应高速缓存线中的数据的推测性修改的推测状态。 响应于在推测性执行指令期间到达特定指令边界时执行的第一操作，推测状态使得对相应高速缓存行中的数据进行推测性修改是永久性的。 此外，推测状态使得能够响应于在推测性执行指令期间不能达到特定指令边界时执行的第二操作来撤消对相应高速缓存行中的数据的推测性修改。

公开(公告)号：US07149851B1

公开(公告)日：2006-12-12

申请号：US10646461

申请日：2003-08-21

申请人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

发明人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC分类号： G06F12/16

CPC分类号： G06F12/0855 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857

摘要： Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.

公开(公告)号：US07225299B1

公开(公告)日：2007-05-29

申请号：US10622028

申请日：2003-07-16

申请人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

发明人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/603

摘要： Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.

摘要翻译： 提供和描述了用于支持数据高速缓存中的推测性修改的方法和系统。 数据高速缓存包括多条高速缓存行。 每个高速缓存线包括用于指示多个状态中的任何一个的状态指示符，其中，所述多个状态包括能够跟踪对相应高速缓存线中的数据的推测性修改的推测状态。 响应于在推测性执行指令期间到达特定指令边界时执行的第一操作，推测状态使得对相应高速缓存行中的数据进行推测性修改是永久性的。 此外，推测状态使得能够响应于在推测性执行指令期间不能达到特定指令边界时执行的第二操作来撤消对相应高速缓存行中的数据的推测性修改。

公开(公告)号：US06604188B1

公开(公告)日：2003-08-05

申请号：US09421972

申请日：1999-10-20

申请人： Brett Coon ,  Godfrey D'Souza ,  Paul Serris

发明人： Brett Coon ,  Godfrey D'Souza ,  Paul Serris

IPC分类号： G06F940

CPC分类号： G06F9/3865 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

摘要： Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action. Applied in a VLIW processor to an atom operation that requires multiple cycles to complete, in which the first part of the operation is permitted to complete and the atom then reasserted, the control information identifies the second assertion of the atom as the second part of a multi-cycle operation.

摘要翻译： 在微处理器的指令流水线（3）中断言的指令伴随着控制信息，包括在处理器的控制信息流水线（15）内断言的一组位。 控制信息流水线与指令流水线同步，使指令的控制信息与指令同步进行。 控制信息可以直接或间接地识别由指令所要求的操作类型，并且如果要以部分执行操作，则指示要执行的部件。 方法包括在处理器中，诸如多个功能执行单元（7），以解释该控制信息并采取适当的动作。 将VLIW处理器应用于需要多个周期来完成的原子操作，其中操作的第一部分被允许完成并且原子然后重新生成，控制信息识别原子的第二个断言作为第二部分 多循环操作。

公开(公告)号：US09645929B2

公开(公告)日：2017-05-09

申请号：US13620070

申请日：2012-09-14

申请人： James Van Zoeren ,  Alexander Klaiber ,  Guillermo J. Rozas ,  Paul Serris

发明人： James Van Zoeren ,  Alexander Klaiber ,  Guillermo J. Rozas ,  Paul Serris

IPC分类号： G06F12/00 ,  G06F12/0831

CPC分类号： G06F12/0831 ,  G06F2212/1024

摘要： In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.

公开(公告)号：US20150149733A1

公开(公告)日：2015-05-28

申请号：US13007015

申请日：2011-01-14

申请人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

发明人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/603

摘要： Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines.

摘要翻译： 提供和描述了用于支持数据高速缓存中的推测性修改的方法和系统。 在一个实施例中，推测性缓存缓冲器包括多个高速缓存行和多个状态指示符。 高速缓存行中的至少一个可操作以从高速缓存接收逐出的高速缓存行。 如果高速缓存请求被驱逐的高速缓存行，则至少一个高速缓存行可操作以将被驱逐的高速缓存行返回到高速缓存。 此外，多个状态指示符可操作以指示高速缓存行的相应高速缓存行的状态。

公开(公告)号：US07886135B1

公开(公告)日：2011-02-08

申请号：US11594672

申请日：2006-11-07

申请人： Brett Coon ,  Godfrey D'Souza ,  Paul Serris

发明人： Brett Coon ,  Godfrey D'Souza ,  Paul Serris

IPC分类号： G06F9/34

CPC分类号： G06F9/3816 ,  G06F9/3824 ,  G06F9/3861

摘要： Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.

摘要翻译： 在微处理器指令流水线（3）中断言的指令伴随着控制信息，包括在与指令流水线同步的控制信息流水线（5）内断言的一组位。 在执行阶段，解释控制信息并采取适当的措施。 控制信息可以指示已经重新指示了指令（在初始断言之后再次断言），并且还可以指示指令在指令流水线中被连续断言的次数。 应用于其中存储器原子被断言两次的未对齐的存储器操作，控制信息指示每次执行原子时将取出未对齐数据的哪一部分。

公开(公告)号：US07725656B1

公开(公告)日：2010-05-25

申请号：US11583463

申请日：2006-10-18

申请人： Guillermo Rozas ,  Alexander Klaiber ,  Robert P. Masleid ,  John Banning ,  James Van Zoeren ,  Paul Serris

发明人： Guillermo Rozas ,  Alexander Klaiber ,  Robert P. Masleid ,  John Banning ,  James Van Zoeren ,  Paul Serris

IPC分类号： G06F13/00

CPC分类号： G06F12/0864

摘要： A method and apparatus for storing and retrieving data in an N-way set associative cache with N data array banks is disclosed. On a cache fill corresponding to a particular way, a portion of each cache line (called a chunk) is placed in each data array bank. On a processor load seeking a requested chunk, a candidate chunk is retrieved from each data array bank and the requested chunk is selected from among the candidates.

摘要翻译： 公开了一种用于在具有N个数据阵列组的N路组合关联高速缓存中存储和检索数据的方法和装置。 在对应于特定方式的缓存填充中，每个高速缓存行（称为块）的一部分被放置在每个数据阵列组中。 在寻求所请求的块的处理器负载上，从每个数据阵列库中检索候选块，并且从候选中选择所请求的块。

公开(公告)号：US09875105B2

公开(公告)日：2018-01-23

申请号：US13463627

申请日：2012-05-03

申请人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

发明人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3863

摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.