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    Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
    1.
    发明授权
    Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine 有权
    为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法和系统

    公开(公告)号：US08041876B1

    公开(公告)日：2011-10-18

    申请号：US11500575

    申请日：2006-08-07

    Applicant: H. Peter Anvin

    Inventor： H. Peter Anvin

    IPC: G06F12/00

    CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F12/145

    Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.

    Abstract translation: 一种为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法。 该方法包括在主机上下文中执行主机应用并且在虚拟机上下文中执行虚拟机应用。 用于虚拟机上下文和主机上下文的多个TLB（转换后备缓冲器）条目存储在TLB内。 逻辑上组合用于多个TLB条目的存储器保护位以在虚拟机应用上实现存储器保护。

    Method and apparatus for improving segmented memory addressing
    6.
    发明授权
    Method and apparatus for improving segmented memory addressing 有权
    改善分段存储器寻址的方法和装置

    公开(公告)号：US06851040B2

    公开(公告)日：2005-02-01

    申请号：US09930625

    申请日：2001-08-15

    Applicant: H. Peter Anvin ,  Alex Klaiber ,  Guillermo J. Rozas ,  Parag Gupta

    Inventor： H. Peter Anvin ,  Alex Klaiber ,  Guillermo J. Rozas ,  Parag Gupta

    IPC: G06F9/26 ,  G06F9/30 ,  G06F9/355 ,  G06F12/00

    CPC classification number: G06F9/355 ,  G06F9/30101

    Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. A method includes providing a first segment selector for deriving a linear address of a segment descriptor in a first descriptor table and providing a second segment selector for deriving a linear address of a segment descriptor in a second descriptor table. The method also includes attempting an access of the first descriptor table to derive a segment descriptor, and if the access of the first descriptor table fails, attempting an access of the second descriptor table to derive a segment descriptor. The method also includes storing a derived segment descriptor from a successful attempted access in a descriptor register.

    Abstract translation: 一种用于将复杂X86段操作和分段存储器寻址分解为显式子操作的方法和装置，以便将其暴露于基于编译器或基于翻译器的优化。 一种方法包括提供第一段选择器，用于在第一描述符表中导出段描述符的线性地址，并提供第二段选择器，用于在第二描述符表中导出段描述符的线性地址。 该方法还包括尝试访问第一描述符表以导出段描述符，并且如果第一描述符表的访问失败，则尝试访问第二描述符表以导出段描述符。 该方法还包括在描述符寄存器中存储来自成功尝试访问的导出段描述符。

    Fine grain translation discrimination
    7.
    发明授权
    Fine grain translation discrimination 有权
    细粮翻译歧视

    公开(公告)号：US06363336B1

    公开(公告)日：2002-03-26

    申请号：US09417356

    申请日：1999-10-13

    Applicant: John Banning ,  H. Peter Anvin ,  Benjamin Gribstad ,  David Keppel ,  Alex Klaiber ,  Paul Serris

    Inventor： John Banning ,  H. Peter Anvin ,  Benjamin Gribstad ,  David Keppel ,  Alex Klaiber ,  Paul Serris

    IPC: G06F900

    CPC classification number: G06F9/3812 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/45504 ,  G06F12/10

    Abstract: A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.

    Abstract translation: 一种用于确定对存储器页面的写入是否被定向到已经被转换为将指令从目标指令集转换到主机指令集的计算机中的主机指令的目标指令的方法，包括以下步骤：检测对存储器页面的写入 将已经被转换为主机指令的目标指令存储在存储器页面中，检测写入的存储器页面的子区域是否存储已被翻译的目标指令，以及使从寻址的目标指令转换的主机指令无效。

    INSTRUCTIONS AND LOGIC TO PROVIDE MEMORY ACCESS KEY PROTECTION FUNCTIONALITY
    8.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE MEMORY ACCESS KEY PROTECTION FUNCTIONALITY 有权
    说明和逻辑提供存储器访问关键保护功能

    公开(公告)号：US20150160998A1

    公开(公告)日：2015-06-11

    申请号：US14099954

    申请日：2013-12-08

    Applicant: H. Peter Anvin ,  Martin G. Dixon

    Inventor： H. Peter Anvin ,  Martin G. Dixon

    IPC: G06F11/10

    CPC classification number: G06F12/1475 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3877 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

    Abstract: Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.

    Abstract translation: 说明和逻辑提供内存密钥保护功能。 实施例包括具有用于存储存储器保护域的寄存器的处理器。 解码器对具有用于存储器操作数的寻址形式字段的指令进行解码以指定一个或多个存储器地址以及存储器保护密钥。 一个或多个执行单元，响应于具有第一值的存储器保护域和具有第二值的解码指令的寻址形式字段，使用指定的存储器保护根据存储器保护字段的所述第一值强制存储器保护 键，用于访问所述一个或多个存储器地址，以及如果由所解码的指令指定的所述存储器保护密钥的一部分与所述一个或多个存储器地址相关联的存储的密钥值不匹配，则发生故障。

    Supporting multiple byte order formats in a computer system
    9.
    发明授权
    Supporting multiple byte order formats in a computer system 有权
    在计算机系统中支持多字节顺序格式

    公开(公告)号：US08458437B2

    公开(公告)日：2013-06-04

    申请号：US13411469

    申请日：2012-03-02

    Applicant: H. Peter Anvin

    Inventor： H. Peter Anvin

    IPC: G06F12/00

    CPC classification number: G06F12/1036 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/1009

    Abstract: Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format.

    Abstract translation: 提供和描述分别或同时支持多字节顺序格式的方法和系统。 在一个实施例中，可编程的页面属性表（PAT）用于指示字节顺序格式。 在另一个实施例中，可编程的存储器类型范围寄存器（MTRR）用于指示字节顺序格式。

    SUPPORTING MULTIPLE BYTE ORDER FORMATS IN A COMPUTER SYSTEM
    10.
    发明申请
    SUPPORTING MULTIPLE BYTE ORDER FORMATS IN A COMPUTER SYSTEM 有权
    支持计算机系统中的多个字节顺序格式

    公开(公告)号：US20120246413A1

    公开(公告)日：2012-09-27

    申请号：US13411469

    申请日：2012-03-02

    Applicant: H. Peter Anvin

    Inventor： H. Peter Anvin

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/1036 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/1009

    Abstract: Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format.

    Abstract translation: 提供和描述分别或同时支持多字节顺序格式的方法和系统。 在一个实施例中，可编程的页面属性表（PAT）用于指示字节顺序格式。 在另一个实施例中，可编程的存储器类型范围寄存器（MTRR）用于指示字节顺序格式。

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