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    System and method of instruction modification
    1.
    发明授权
    System and method of instruction modification 有权
    指令修改的系统和方法

    公开(公告)号：US08549266B2

    公开(公告)日：2013-10-01

    申请号：US13155291

    申请日：2011-06-07

    Applicant: John P. Banning ,  Eric Hao ,  Brett Coon

    Inventor： John P. Banning ,  Eric Hao ,  Brett Coon

    IPC: G06F9/30

    CPC classification number: G06F9/3017

    Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

    Abstract translation: 可以获取可以包括多个离散指令的第一机器语言指令。 响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。 信息可以根据触发模式中概述的细节代替到细分。 或者，可以通过逻辑和/或算术运算将信息与段组合。 段的修改产生由处理器的单元执行的第二机器语言指令。 在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。 如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

    HISTORY BASED PIPELINED BRANCH PREDICTION
    3.
    发明申请
    HISTORY BASED PIPELINED BRANCH PREDICTION 有权
    基于历史的管道分支预测

    公开(公告)号：US20120072708A1

    公开(公告)日：2012-03-22

    申请号：US12851906

    申请日：2010-08-06

    Applicant: David A. Dunn ,  John P. Banning

    Inventor： David A. Dunn ,  John P. Banning

    IPC: G06F9/38

    CPC classification number: G06F9/3844 ,  G06F9/3806

    Abstract: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

    Abstract translation: 基于历史的流水线分支预测的系统和方法。 在一个实施例中，访问预测信息以预测指令块内的多个分支在计算机处理器的相同时钟周期中作为指令块的获取发起。 预测信息可以在不晚于其中解码多个分支的计算机处理器的时钟周期的情况下对预测器可用。

    History based pipelined branch prediction
    5.
    发明授权
    History based pipelined branch prediction 有权
    基于历史的流水线分支预测

    公开(公告)号：US07779241B1

    公开(公告)日：2010-08-17

    申请号：US11786336

    申请日：2007-04-10

    Applicant: David A. Dunn ,  John P. Banning

    Inventor： David A. Dunn ,  John P. Banning

    IPC: G06F9/32

    CPC classification number: G06F9/3844 ,  G06F9/3806

    Abstract: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

    Abstract translation: 基于历史的流水线分支预测的系统和方法。 在一个实施例中，访问预测信息以预测指令块内的多个分支在计算机处理器的相同时钟周期中作为指令块的获取发起。 预测信息可以在不晚于其中解码多个分支的计算机处理器的时钟周期的情况下对预测器可用。

    Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
    8.
    发明授权
    Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit 失效
    具有片上缓存和片上存储器管理单元的流水线单片微处理器

    公开(公告)号：US4794524A

    公开(公告)日：1988-12-27

    申请号：US627475

    申请日：1984-07-03

    Applicant: Richard A. Carberry ,  John P. Banning

    Inventor： Richard A. Carberry ,  John P. Banning

    IPC: G06F9/38 ,  G06F12/10 ,  G06F15/78 ,  G06F9/00

    CPC classification number: G06F9/3867 ,  G06F12/1054 ,  G06F15/7846

    Abstract: A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.

    Abstract translation: 具有六级流水线架构的32位中央处理单元，具有高速缓冲存储器和存储器管理单元，其全部提供在单个集成电路（IC）芯片上，但没有任何外围接口输入/输出电路，芯片上的时钟或类似电路 以便利用有限的IC 实现最直接影响操作速度和其他性能因素的处理器功能的区域。

    History based pipelined branch prediction
    9.
    发明授权
    History based pipelined branch prediction 有权
    基于历史的流水线分支预测

    公开(公告)号：US08473727B2

    公开(公告)日：2013-06-25

    申请号：US12851906

    申请日：2010-08-06

    Applicant: David A. Dunn ,  John P. Banning

    Inventor： David A. Dunn ,  John P. Banning

    IPC: G06F9/42

    CPC classification number: G06F9/3844 ,  G06F9/3806

    Abstract: Systems and methods for history based pipelined branch prediction. In one example, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

    Abstract translation: 基于历史的流水线分支预测的系统和方法。 在一个示例中，访问预测信息以预测指令块内的多个分支在计算机处理器的与指令块的获取相同的时钟周期中被起始。 预测信息可以在不晚于其中解码多个分支的计算机处理器的时钟周期的情况下对预测器可用。

    System and method of instruction modification
    10.
    发明授权
    System and method of instruction modification 有权
    指令修改的系统和方法

    公开(公告)号：US07698539B1

    公开(公告)日：2010-04-13

    申请号：US10672790

    申请日：2003-09-26

    Applicant: John P. Banning ,  Eric Hao ,  Brett Coon

    Inventor： John P. Banning ,  Eric Hao ,  Brett Coon

    IPC: G06F9/30

    CPC classification number: G06F9/3017

    Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

    Abstract translation: 指令修改的方法和系统。 可以获取可以包括多个离散指令的第一机器语言指令。 响应于第一机器语言指令中的触发模式，第一机器语言指令的段被修改。 信息可以根据触发模式中概述的细节代替到细分。 或者，可以通过逻辑和/或算术运算将信息与段组合。 段的修改产生由处理器的单元执行的第二机器语言指令。 在一个实施例中，可以从队列中获取信息，并用于替换来自段的数据。 如何从队列中获取信息，以及如何使用如此使用的信息来替换段的字段由触发模式定义。

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