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1.发明授权Instruction and logic to provide vector horizontal majority voting functionality 有权提供向量横向多数投票功能的指令和逻辑公开(公告)号：US09448794B2
公开(公告)日：2016-09-20
申请号：US13977735
申请日：2011-11-30
CPC分类号： G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
摘要： Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要翻译： 指令和逻辑提供向量横向多数投票功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数 从源操作数的数据字段数读取的值。
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2.发明申请INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOAD-OP/STORE-OP WITH STRIDE FUNCTIONALITY 有权指令和逻辑提供向量负载/存储 - 具有强大的功能公开(公告)号：US20140195778A1
公开(公告)日：2014-07-10
申请号：US13977728
申请日：2011-09-26
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F9/30185 , G06F9/3455 , G06F9/3808 , G06F9/3877 , G06F9/3887 , G06F15/8061
摘要： Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.
摘要翻译： 指令和逻辑提供矢量加载操作和/或存储操作与步幅功能。 一些实施例，响应于指令：一组负载，第二操作，目的地寄存器，操作数寄存器，存储器地址和步幅长度; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的跨距长度倍数。 第一个掩码值表示元素尚未从内存中加载，第二个值表示元素不需要或已经被加载。 对于具有第一个值的每一个，数据元素从存储器加载到相应的目标寄存器位置，并且掩码寄存器中的对应值被改变为第二值。 然后使用目的地和操作数寄存器中的相应数据执行第二个操作，以生成结果。 指令可能在故障后重新启动。
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公开(公告)号：US09946541B2
公开(公告)日：2018-04-17
申请号：US14975612
申请日：2015-12-18
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30181 , G06F9/30192 , G06F9/3455
摘要： Systems, methods, and apparatuses for strided access are described. In some embodiments, a plurality of registers are loaded with data from an array of structures. Then data elements that that are not needed in a permute operation are overwritten with index values with a write mask. The register now contains a mix of data and index values. When this same write mask is passed to the permute instruction which overwrites the index register as destination, the data values are preserved and index values are overwritten with data coming from the other two source registers as controlled by the index values.
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公开(公告)号：US20170185465A1
公开(公告)日：2017-06-29
申请号：US14983026
申请日：2015-12-29
CPC分类号： G06F11/079 , G06F9/3001 , G06F9/30036 , G06F9/30189 , G06F9/30196 , G06F9/3861 , G06F9/3889 , G06F9/455 , G06F11/0745 , G06F11/0751 , G06F11/0772 , G06F11/1608 , G06F11/1629 , G06F11/1641 , G06F15/8007
摘要： Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.
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公开(公告)号：US09672036B2
公开(公告)日：2017-06-06
申请号：US13977730
申请日：2011-09-26
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.
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公开(公告)号：US09632980B2
公开(公告)日：2017-04-25
申请号：US13976435
申请日：2011-12-23
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F15/8092
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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公开(公告)号：US09459866B2
公开(公告)日：2016-10-04
申请号：US13993058
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/3016 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要翻译： 一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。 源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。 目标操作数标识目标向量寄存器。 处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。 源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定压缩值，后跟该运行的运行长度。
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8.发明申请公开(公告)号：US20170269935A1
公开(公告)日：2017-09-21
申请号：US15612204
申请日：2017-06-02
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. In one implementation, a processor is provided that includes decode circuitry to decode an instruction specifying a memory address and a stride length for a set of load operations corresponding to a first plurality of data elements of a destination register. The processor further includes one or more execution units, responsive to the decoded first instruction, to load a first data element from the memory address into a first data element of the destination register, and load a second data element from a memory address that is non-zero multiple of the stride length into a first data element of the destination register.
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公开(公告)号：US09747101B2
公开(公告)日：2017-08-29
申请号：US13977729
申请日：2011-09-26
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/30145 , G06F9/3836 , G06F15/8061
摘要： Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.
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公开(公告)号：US09575757B2
公开(公告)日：2017-02-21
申请号：US13991858
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译： 一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。 执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。 第二个掩码基于尾随零的计数。 执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。 将缓冲区移位并复制到结果，并将源数据元素集合向右移动。 如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。
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