公开(公告)号：US20190188093A1

公开(公告)日：2019-06-20

申请号：US16324587

申请日：2017-07-24

申请人： SIEMENS MOBILITY GMBH

发明人： UWE ECKELMANN-WENDT ,  STEFAN GERKEN

IPC分类号： G06F11/16 ,  G06F11/28 ,  G06F17/50

CPC分类号： G06F11/1641 ,  G06F11/28 ,  G06F17/5054 ,  G06F2201/83 ,  G06F2201/845

摘要： An arrangement for redundant data processing has an integrated circuit in which the functionality of a multi-core processor is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program. The results which emerge from the execution of the useful program by the different processor cores are compared by a comparison module of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) that is assigned to the particular processor core. In terms of hardware, the individual processor cores are at least partially implemented separately in the integrated circuit.

公开(公告)号：US20190155325A1

公开(公告)日：2019-05-23

申请号：US15819402

申请日：2017-11-21

申请人： The Boeing Company

发明人： Wing C. Lee ,  Sean M. Ramey ,  Ronald James Koontz ,  Dick P. Wong ,  Jackson Chia ,  Anthony S. Fornabaio ,  Murali Rangarajan ,  Clarke Edgar Moore ,  David Clyde Sharp ,  Arnold W. Nordsieck ,  Paul Eugene Denzel

IPC分类号： G06F1/10 ,  G06F1/12

CPC分类号： G06F1/10 ,  G06F1/12 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/1683 ,  G06F11/1695

摘要： A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

公开(公告)号：US20190079826A1

公开(公告)日：2019-03-14

申请号：US15704661

申请日：2017-09-14

申请人： BAE Systems Controls Inc.

发明人： Dino A. Gianisis ,  Michael G. Adams

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G05B9/03 ,  G06F11/0721 ,  G06F11/1633 ,  G06F11/1641 ,  G06F11/2028 ,  G06F12/0842 ,  G06F13/4282 ,  G06F2212/1032 ,  G06F2212/62

摘要： A control system includes a computing channel and an object control channel. The computing channel includes command and monitor lanes. The command lane has a first processor core with a first core architecture receiving input data and generating first data based on the input data. The monitor lane has a second processor core with second core architecture receiving the input data and generating second data based on the input data. The first core architecture and the second core architecture are dissimilar and implemented in a single system-on chip device. The computing channel outputs the first data as command data responsive to determining the first data is matched to the second data. The object control channel corresponds to the computing channel and includes an object control system receiving the command data and generating an object control signal based on the command data to control operation of at least one part of an object system.

公开(公告)号：US20180322021A1

公开(公告)日：2018-11-08

申请号：US16036906

申请日：2018-07-16

申请人： Arteris, Inc.

发明人： Benoit de LESCURE ,  Jean Philippe LOISON ,  Alexis BOUTILLER

IPC分类号： G06F11/16 ,  G06F12/0837 ,  G06F11/07 ,  G06F12/0815

CPC分类号： G06F11/1666 ,  G06F11/079 ,  G06F11/1641 ,  G06F11/1695 ,  G06F12/0815 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/60

摘要： A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects

公开(公告)号：US20180267868A1

公开(公告)日：2018-09-20

申请号：US15832251

申请日：2017-12-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Jingwen Leng ,  Ramon Bertran Monfort

IPC分类号： G06F11/16

CPC分类号： G06F11/1658 ,  G06F11/1629 ,  G06F11/1641 ,  G06F2201/805 ,  G06F2201/82

摘要： A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures. The method additionally includes performing an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.

公开(公告)号：US20180267866A1

公开(公告)日：2018-09-20

申请号：US15463066

申请日：2017-03-20

申请人： ARM Limited

发明人： Balaji VENU ,  Xabier ITURBE ,  Emre ÖZER

IPC分类号： G06F11/16 ,  G06F11/18

CPC分类号： G06F11/1641 ,  G06F11/1629 ,  G06F11/184

摘要： An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.

公开(公告)号：US10025677B2

公开(公告)日：2018-07-17

申请号：US15387625

申请日：2016-12-21

申请人： Arteris, Inc.

发明人： Benoit de Lescure ,  Jean Philippe Loison ,  Alexis Boutiller

IPC分类号： G06F7/02 ,  H03M13/00 ,  G06F11/16 ,  G06F12/0837

CPC分类号： G06F11/1666 ,  G06F11/079 ,  G06F11/1641 ,  G06F11/1695 ,  G06F12/0815 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/60

摘要： A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

公开(公告)号：US09956973B2

公开(公告)日：2018-05-01

申请号：US14791785

申请日：2015-07-06

申请人： Westinghouse Air Brake Technologies Corporation

发明人： Kristofer M. Ruhland ,  Kendrick W. Gawne ,  James L. Fenske

IPC分类号： G06F11/16 ,  B61L15/00

CPC分类号： B61L15/0018 ,  B61L15/0027 ,  B61L15/0036 ,  B61L15/0063 ,  B61L15/0072 ,  B61L15/0081 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/167

摘要： A system, method, and apparatus for generating vital messages on an on-board system of a vehicle is disclosed. The method includes generating a plurality of vital messages with each processor of a plurality of different processors of the on-board system based on train data available to each processor, transmitting the plurality of vital messages from the plurality of different processors to a separate processor, and generating, by the separate processor, a final vital message based on at least two vital messages of the plurality of vital messages. A system and an apparatus for implementing the aforementioned method includes appropriately communicatively connected hardware components.

公开(公告)号：US09935539B2

公开(公告)日：2018-04-03

申请号：US14827098

申请日：2015-08-14

申请人： Zodiac Aero Electric

发明人： Jean-Clair Pradier ,  Stéphane Guenot

IPC分类号： B60L1/00 ,  B60L3/00 ,  H02G3/00 ,  H02M3/04 ,  B64D47/00 ,  H02J3/00 ,  G06F11/16 ,  H03K17/18 ,  H03K17/691 ,  G06F11/18 ,  H02H1/00 ,  H02H3/08 ,  H02H5/04

CPC分类号： H02M3/04 ,  B64D47/00 ,  G06F11/1641 ,  G06F11/182 ,  H02H1/0015 ,  H02H1/0092 ,  H02H3/08 ,  H02H5/04 ,  H02J3/00 ,  H03K17/18 ,  H03K17/691

摘要： System, especially for use in aircraft, for controlling at least one switching device (5, 5b, 5n) able to open or close the connection between at least one power source and at least one supplied device, and means for measuring the state of the power supply channel. The system comprises: at least two microcontrollers (1a, 1b) each able to emit a command intended for each switching device (5, 5b, 5n), said microcontrollers (1a, 1b) being connected to at least one portion of the means for measuring the state of the power supply channel; and a means (14, 14b, 14n) for determining the command to be transmitted, able to determine the command to be transmitted to each switching device (5, 5b, 5n) from the commands emitted by each microcontroller (1a, 1b) and intended for said control switch.

公开(公告)号：US20180067882A1

公开(公告)日：2018-03-08

申请号：US15811414

申请日：2017-11-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kenji KIMURA

IPC分类号： G06F13/364 ,  G06F11/14 ,  G06F11/18

CPC分类号： G06F13/364 ,  G06F11/0757 ,  G06F11/0766 ,  G06F11/0796 ,  G06F11/14 ,  G06F11/1641 ,  G06F11/1683 ,  G06F11/181 ,  G06F11/184 ,  G06F2201/845

摘要： The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.