公开(公告)号：US20200004959A1

公开(公告)日：2020-01-02

申请号：US16456578

申请日：2019-06-28

Applicant: Robert S. Chappell ,  Jared W. STARK, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

Inventor： Robert S. Chappell ,  Jared W. STARK, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F9/30 ,  G06F12/0802

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US09524263B2

公开(公告)日：2016-12-20

申请号：US13538463

申请日：2012-06-29

Applicant: Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

Inventor： Robert S. Chappell ,  John W. Faistl ,  Hermann W. Gartler ,  Michael D. Tucknott ,  Rajesh S. Parathasarthy ,  David W. Burns

IPC: G06F13/42 ,  G06F9/52 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Abstract translation: 描述了一种包括检测线程的指令是锁定指令的方法。 该指令还包括确定所述指令的执行包括施加总线锁定。 该指令还包括响应于所述确定执行总线锁定辅助功能，所述总线锁定辅助功能包括除了总线锁定协议的实现之外的与所述总线锁相关联的功能。

公开(公告)号：US20160154648A1

公开(公告)日：2016-06-02

申请号：US14998118

申请日：2015-12-26

Applicant: Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Abstract translation: 本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。 硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件， 或其组合基于跟踪的中止事件进行中止判定。 作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。 在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。 并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

公开(公告)号：US20160132337A1

公开(公告)日：2016-05-12

申请号：US14998296

申请日：2015-12-26

Applicant: Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US20160132334A1

公开(公告)日：2016-05-12

申请号：US14998250

申请日：2015-12-26

Applicant: Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Abstract translation: 本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。 硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件， 或其组合基于跟踪的中止事件进行中止判定。 作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。 在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。 并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

公开(公告)号：US08838935B2

公开(公告)日：2014-09-16

申请号：US12890585

申请日：2010-09-24

Applicant: Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

Inventor： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Abstract translation: 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

公开(公告)号：US20140095814A1

公开(公告)日：2014-04-03

申请号：US13631644

申请日：2012-09-28

Applicant: MORRIS MARDEN ,  VIJAYKUMAR VIJAY KADGI ,  JAMES D. HADLEY ,  MATTHEW C. MERTEN ,  GRACE C. LEE ,  JOSEPH A. MCMAHON ,  ROBERT S. CHAPPELL ,  LAURA A. KNAUTH ,  FARIBORZ TABESH

Inventor： MORRIS MARDEN ,  VIJAYKUMAR VIJAY KADGI ,  JAMES D. HADLEY ,  MATTHEW C. MERTEN ,  GRACE C. LEE ,  JOSEPH A. MCMAHON ,  ROBERT S. CHAPPELL ,  LAURA A. KNAUTH ,  FARIBORZ TABESH

IPC: G06F12/00

CPC classification number: G06F9/384 ,  G06F9/30043

Abstract: A processor includes a processing unit including a storage module having stored thereon a table for tracking physical registers in which each store operation stores source data and a memory renaming module for register renaming load operations based on the table.

Abstract translation: 处理器包括处理单元，该处理单元包括存储模块，存储模块用于跟踪物理寄存器，其中每个存储操作存储源数据，以及用于基于该表进行寄存器重命名加载操作的存储器重命名模块。

公开(公告)号：US20140075123A1

公开(公告)日：2014-03-13

申请号：US13613777

申请日：2012-09-13

Applicant: Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

Inventor： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者， 逻辑，用于防止第一步行者将所获得的物理地址部分存储在响应于第一线性地址部分匹配第二步行者的并发寻呼结构访问的相应线性地址部分的寻呼高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US20120072984A1

公开(公告)日：2012-03-22

申请号：US12887898

申请日：2010-09-22

Applicant: MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

Inventor： MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC: G06F21/00

CPC classification number: G06F9/526

Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US20110161595A1

公开(公告)日：2011-06-30

申请号：US12647461

申请日：2009-12-26

Applicant: Zhen Fang ,  Meenakshisundara R. Chinthamani ,  Li Zhao ,  Milind B. Kamble ,  Ravishankar Iyer ,  Seung Eun Lee ,  Robert S. Chappell ,  Ryan L. Carlson

Inventor： Zhen Fang ,  Meenakshisundara R. Chinthamani ,  Li Zhao ,  Milind B. Kamble ,  Ravishankar Iyer ,  Seung Eun Lee ,  Robert S. Chappell ,  Ryan L. Carlson

IPC: G06F12/08 ,  G06F12/00 ,  G06F1/32

CPC classification number: G06F12/0864 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.

Abstract translation: 描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。 在一个实施例中，使用虚拟标签来确定是否访问缓存方式。 虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。 在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。 还描述了其它实施例。