公开(公告)号：US20160132336A1

公开(公告)日：2016-05-12

申请号：US14998276

申请日：2015-12-26

Applicant: Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US08972994B2

公开(公告)日：2015-03-03

申请号：US12645668

申请日：2009-12-23

Applicant: Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

Inventor： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

IPC: G06F9/44 ,  G06F9/46 ,  G06F9/52 ,  G06F9/455 ,  G06F17/30 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/528 ,  G06F8/458 ,  G06F9/3842 ,  G06F9/45516 ,  G06F9/526 ,  G06F17/30168 ,  G06F17/30362 ,  Y10S707/99938

Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

Abstract translation: 公开了用于管理对象锁的示例性方法和装置。 所公开的示例性方法包括从处理器接收对象锁定请求，与对象锁定代码相关联的锁定请求以锁定对象，以及基于处理器的类型生成对象锁定旁路代码，执行对象锁定旁路代码 在受管运行时响应于接收到对象锁定请求。 示例性方法还包括识别与处理器相关联的指令集架构（ISA）的类型，基于所识别的ISA调用处理器的检查点指令，当对象不受约束时暂停对象锁定代码执行和执行目标代码， 并允许对象锁定代码在对象被竞争时执行。

公开(公告)号：US20150006496A1

公开(公告)日：2015-01-01

申请号：US13931860

申请日：2013-06-29

Applicant: Ravi RAJWAR ,  Matthew C. MERTEN ,  Christine E. WANG ,  Vijaykumar B. KADGI ,  Rajesh S. PARTHASARATHY

Inventor： Ravi RAJWAR ,  Matthew C. MERTEN ,  Christine E. WANG ,  Vijaykumar B. KADGI ,  Rajesh S. PARTHASARATHY

IPC: G06F9/46

CPC classification number: G06F9/467 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F9/528

Abstract: A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Abstract translation: 描述了处理器，系统和方法，用于在提交程序代码的推测区域期间继续退出操作。 例如，方法的一个实施例包括在程序代码中识别多个事务存储区域的操作，包括第一事务存储器区域; 以及即使当与第一事务存储器区域相关联的提交操作等待完成时，退出遵循第一事务存储器区域的多个操作中的一个或多个操作。

公开(公告)号：US20140379996A1

公开(公告)日：2014-12-25

申请号：US13997245

申请日：2012-02-02

Applicant: Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

Inventor： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

IPC: G06F9/52 ,  G06F12/08 ,  G06F9/46

Abstract: An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.

Abstract translation: 这里描述了一种用于提供推测逃逸指令的装置和方法。 具体地，本文描述了显式的非事务性加载操作。 在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。 然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。 同样，也提供非事务存储。 这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。 并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。 换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。

公开(公告)号：US08881106B2

公开(公告)日：2014-11-04

申请号：US12978480

申请日：2010-12-24

Applicant: Peter Lachner ,  Konrad K. Lai ,  Ravi Rajwar

Inventor： Peter Lachner ,  Konrad K. Lai ,  Ravi Rajwar

IPC: G06F9/44 ,  G06F11/36 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3861 ,  G06F11/362

Abstract: Methods and apparatus relating to debugging parallel software using speculatively executed code sequences in a multiple core environment are described. In an embodiment, occurrence of a speculative code debug event is detected and a speculative code execution debug module is executed in response to occurrence of the event. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了在多核心环境中使用推测执行的代码序列调试并行软件的方法和装置。 在一个实施例中，检测到推测代码调试事件的发生，并且响应于事件的发生而执行推测代码执行调试模块。 还公开并要求保护其他实施例。

公开(公告)号：US20110225375A1

公开(公告)日：2011-09-15

申请号：US13113432

申请日：2011-05-23

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US20110161639A1

公开(公告)日：2011-06-30

申请号：US12655204

申请日：2009-12-26

Applicant: Laura A. Knauth ,  Ravi Rajwar ,  Konrad K. Lai ,  Martin G. Dixon ,  Peggy Irelan

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Konrad K. Lai ,  Martin G. Dixon ,  Peggy Irelan

IPC: G06F9/312 ,  G06F9/38

CPC classification number: G06F11/1469 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F11/1451 ,  G06F11/3466 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

Abstract: A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.

Abstract translation: 一个方面的方法可以包括存储事件计数器的事件计数器，其计数在逻辑设备内执行期间发生的事件。 该方法还可以包括在事件计数器计数附加事件之后恢复事件计数器到所存储的事件计数。 还公开了其它方法。 还公开了具有软件的装置，系统和机器可读介质。

公开(公告)号：US07962699B2

公开(公告)日：2011-06-14

申请号：US12843828

申请日：2010-07-26

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US20080115042A1

公开(公告)日：2008-05-15

申请号：US11599009

申请日：2006-11-13

Applicant: Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

Inventor： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

IPC: H03M13/51

CPC classification number: G06F9/3865 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/528

Abstract: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.

Abstract translation: 这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。 检测逻辑检测到锁定指令，这可能存在于解码逻辑中。 存储/创建与锁定指令相关联的锁定指令条目。 将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。 如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。 预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值 指令。

公开(公告)号：US20070143550A1

公开(公告)日：2007-06-21

申请号：US11313114

申请日：2005-12-19

Applicant: Ravi Rajwar ,  Matthew Mattina

Inventor： Ravi Rajwar ,  Matthew Mattina

IPC: G06F13/28

CPC classification number: G06F12/0811 ,  G06F12/084

Abstract: A multi-core processor includes a plurality of processors and a shared cache. Cache control logic implements an inclusive cache scheme among the shared cache and the local caches for the processors. Counters are maintained to track instances, per set, when a processor chooses to delay eviction from the local cache. While the counter indicates that one or more delayed evictions are pending for a set, the cache control logic treats the set as non-inclusive, broadcasting foreign snoops to all of the local caches, regardless of whether the snoop hits in the shared cache. Other embodiments are also described and claimed.

Abstract translation: 多核处理器包括多个处理器和共享高速缓存。 缓存控制逻辑在共享高速缓存和处理器的本地高速缓存之间实现包容性高速缓存方案。 当处理器选择延迟从本地缓存驱逐时，计数器被维护以跟踪每集的实例。 虽然计数器指示一个或多个延迟的撤离正在等待一组，但是高速缓存控制逻辑将该集合视为非包容性，将广播外部侦听广播到所有本地高速缓存，而不管窥探者是否在共享高速缓存中命中。 还描述和要求保护其他实施例。