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    Methods and apparatus for efficient communication between caches in hierarchical caching design
    1.
    发明授权
    Methods and apparatus for efficient communication between caches in hierarchical caching design 有权
    用于层次化缓存设计中高速缓存之间高效通信的方法和设备

    公开(公告)号：US09411728B2

    公开(公告)日：2016-08-09

    申请号：US13994399

    申请日：2011-12-23

    Applicant: Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

    Inventor： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

    IPC: G06F13/00 ,  G06F12/08 ,  G06F13/14 ,  G06F13/38

    CPC classification number: G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

    Abstract translation: 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

    Balanced P-LRU tree for a “multiple of 3” number of ways cache
    2.
    发明授权
    Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
    平衡的P-LRU树为“多个3”的缓存方式

    公开(公告)号：US09348766B2

    公开(公告)日：2016-05-24

    申请号：US13994690

    申请日：2011-12-21

    Applicant: Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    Inventor： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC: G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    Abstract translation: 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

    Protecting the integrity of binary translated code
    3.
    发明授权
    Protecting the integrity of binary translated code 有权
    保护二进制翻译代码的完整性

    公开(公告)号：US09027009B2

    公开(公告)日：2015-05-05

    申请号：US13991894

    申请日：2011-12-29

    Applicant: Shlomo Raikin ,  Lihu Rappoport ,  Joseph Nuzman

    Inventor： Shlomo Raikin ,  Lihu Rappoport ,  Joseph Nuzman

    IPC: G06F9/45 ,  G06F21/64

    CPC classification number: G06F8/41 ,  G06F8/52 ,  G06F21/64

    Abstract: The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.

    Abstract translation: 本文提供的技术涉及保护已经优化的原始代码的完整性。 例如，处理器可以执行取出操作以从存储器获得指定的代码。 在执行期间，代码可以被优化并存储在存储器的一部分中。 处理器可以从存储器的一部分获得优化的代码。 可以修改第一表的条目以指示特定代码和优化的代码之间的关系。 可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。 第二表中的一个或多个条目中的每一个可对应于第一表的条目。 当第二表的一个或多个条目中的每一个有效时，处理器可以执行优化的代码。

    METHODS AND APPARATUS FOR EFFICIENT COMMUNICATION BETWEEN CACHES IN HIERARCHICAL CACHING DESIGN
    6.
    发明申请
    METHODS AND APPARATUS FOR EFFICIENT COMMUNICATION BETWEEN CACHES IN HIERARCHICAL CACHING DESIGN 有权
    用于分层缓存设计中的高速缓存之间的有效通信的方法和设备

    公开(公告)号：US20130326145A1

    公开(公告)日：2013-12-05

    申请号：US13994399

    申请日：2011-12-23

    Applicant: Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

    Inventor： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

    Abstract translation: 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

    Live lock free priority scheme for memory transactions in transactional memory
    7.
    发明授权
    Live lock free priority scheme for memory transactions in transactional memory 有权
    事务内存中的内存事务的实时锁定优先级方案

    公开(公告)号：US08209689B2

    公开(公告)日：2012-06-26

    申请号：US11854175

    申请日：2007-09-12

    Applicant: Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

    Inventor： Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

    IPC: G06F9/52 ,  G06F13/14 ,  G06F12/00 ,  G06F7/00 ,  G06F13/00

    CPC classification number: G06F9/524 ,  G06F9/466

    Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.

    Abstract translation: 这里描述了用于在事务执行期间避免实时锁定的方法和装置。 计数逻辑用于跟踪每个处理元素的成功提交事务。 当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。 此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。 为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。 此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。 当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

    Protected cache architecture and secure programming paradigm to protect applications
    10.
    发明授权
    Protected cache architecture and secure programming paradigm to protect applications 有权
    保护缓存架构和安全编程范例来保护应用程序

    公开(公告)号：US07958320B2

    公开(公告)日：2011-06-07

    申请号：US11998902

    申请日：2007-12-03

    Applicant: Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

    Inventor： Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

    IPC: G06F12/06

    CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/1491 ,  G06F21/10

    Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.

    Abstract translation: 本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。 受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。 描述和要求保护其他实施例。

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