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公开(公告)号：US20190179767A1
公开(公告)日：2019-06-13
申请号：US15840507
申请日：2017-12-13
申请人： Red Hat, Inc.
IPC分类号： G06F12/1009 , G06F9/455
CPC分类号： G06F12/1009 , G06F9/45558 , G06F2212/655 , G06F2212/657
摘要： A system and method relates to detecting a hardware event, determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread, identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file, identifying a memory address table associated with the file descriptor, translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread, and transmitting, to the second processing thread, a notification comprising the second virtual memory address.
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公开(公告)号：US09934100B2
公开(公告)日：2018-04-03
申请号：US14637955
申请日：2015-03-04
发明人： Sun-Young Lim , Sung-Yong Seo , Young-Jin Cho , Ju-Yun Jung
IPC分类号： G06F13/36 , G06F11/14 , G06F13/28 , G06F12/08 , G06F12/1009 , G06F12/121
CPC分类号： G06F11/1446 , G06F12/08 , G06F12/1009 , G06F12/121 , G06F13/28 , G06F2212/655
摘要： A memory swap operation comprises writing information about a process in which a page fault occurred, into a temporary memory using a processor of a host, copying a page in which the page fault occurred, from a memory device recognized as a swap memory into a main memory of the host, and after completing the copying of the page, resuming the process in which the page fault occurred, using the information about the process, written in the temporary memory.
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公开(公告)号：US20140149679A1
公开(公告)日：2014-05-29
申请号：US13686799
申请日：2012-11-27
申请人： NVIDIA CORPORATION
发明人： Joseph Rowlands , Anurag Chaudhary
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/1024 , G06F2212/6026 , G06F2212/655
摘要： Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.
摘要翻译： 预取可以从一个物理内存页到另一个物理内存页。 更具体地，如果访问请求流包含映射到多于一个物理存储器页面的虚拟地址，则预取可以从第一物理存储器页继续到第二物理存储器页。 基于当第一物理存储器页面是访问请求的目标时建立的置信水平和预取距离，预取有利地继续到第二物理存储器页面。
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4.发明申请Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode 失效在Base Plus偏移寻址模式中将虚拟地址转换为物理地址的装置和方法公开(公告)号：US20100228944A1
公开(公告)日：2010-09-09
申请号：US12397438
申请日：2009-03-04
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译： 公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。 在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。 在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。 该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。
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公开(公告)号：US07404042B2
公开(公告)日：2008-07-22
申请号：US11132749
申请日：2005-05-18
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译： 处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。 指令可能会跨越缓存行边界。 流水线处理两个地址以恢复完整的边界交叉指令。 在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。 在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。 当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。
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公开(公告)号：US06961837B2
公开(公告)日：2005-11-01
申请号：US10396585
申请日：2003-03-25
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1081 , G06F2212/654 , G06F2212/655
摘要： An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.
摘要翻译： 检测到队列结束或队列中的页面跨越。 队列头部或下一个队列页面的虚拟内存地址在服务队列或当前队列页面中的最后一个条目时被预先转换为物理内存地址。
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公开(公告)号：US3800291A
公开(公告)日：1974-03-26
申请号：US29110372
申请日：1972-09-21
申请人： IBM
CPC分类号： G06F12/10 , G06F9/24 , G06F2212/655
摘要： A data processing system having a virtual memory comprising pages which are relocatable between various levels of physical storage. The virtual memory primarily contains information comprising instructions arranged sequentially so that once a virtual address has been translated to the physical address in high speed memory, the physical address can be incremented to fetch the next sequential information. Branch instructions may branch to the address of information on the same or another page. The branch instruction includes an indicator as to whether the branch address is a physical address on the same or another page or a virtual address on another page. Only when a virtual address is encountered is the relocation table employed to convert the virtual address to a physical address and to load the page if necessary.
摘要翻译： 一种具有虚拟存储器的数据处理系统，该虚拟存储器包括可在不同级别的物理存储之间重新定位的页面。 虚拟存储器主要包含包括按顺序布置的指令的信息，使得一旦虚拟地址已经被转换到高速存储器中的物理地址，则可以增加物理地址以获取下一个顺序信息。 分支指示可以分支到相同或另一页面上的信息的地址。 分支指令包括关于分支地址是相同或另一页面上的物理地址还是在另一页面上的虚拟地址的指示符。 只有当遇到虚拟地址时，才使用重定位表来将虚拟地址转换为物理地址，并在必要时加载页面。
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公开(公告)号：US3768080A
公开(公告)日：1973-10-23
申请号：US3768080D
申请日：1972-01-20
申请人： IBM
CPC分类号： G06F12/1036 , G06F2212/655
摘要： In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.
摘要翻译： 在微程序处理器中，布置了一对寄存器装置和关联存储器，以消除将每个微指令将逻辑地址转换为访问主存储器的真实地址的需要。 对于每个程序或机器级（宏）指令，翻译仅需要一次。 当前指令的第一个字节的实际地址及其操作数存储在寄存器装置的第一个字节中，并且通常递增，以逐字节访问指令和操作数的剩余部分。 此外，第一寄存器装置和递增器可用于以程序序列访问顺序存储的指令而不进行地址转换。 当在所述递增期间跨越页边界时，从第二寄存器装置读取当前指令或操作数（在边界处）的逻辑页地址，并增加以形成下一顺序页的逻辑地址。 在关联数组中搜索新的逻辑地址。 如果发生匹配，则新的逻辑地址被存储在第二寄存器装置中，并且相应的实际地址被存储在第一寄存器装置中。 这个硬件翻译手段大大减少了翻译时间。
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公开(公告)号：US20240160576A1
公开(公告)日：2024-05-16
申请号：US18054249
申请日：2022-11-10
IPC分类号： G06F12/1009
CPC分类号： G06F12/1009 , G06F2212/1028 , G06F2212/655
摘要： Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.
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公开(公告)号：US11966341B1
公开(公告)日：2024-04-23
申请号：US18054249
申请日：2022-11-10
IPC分类号： G06F12/1009
CPC分类号： G06F12/1009 , G06F2212/1028 , G06F2212/655
摘要： Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.
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