公开(公告)号：US20190236019A1

公开(公告)日：2019-08-01

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/0215 ,  G06F12/1036 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/68

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

公开(公告)号：US20190213126A1

公开(公告)日：2019-07-11

申请号：US16357719

申请日：2019-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

IPC: G06F12/02 ,  G06F12/1036 ,  G06F3/06 ,  G06F9/455 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1009

CPC classification number: G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

Abstract: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

公开(公告)号：US10083126B2

公开(公告)日：2018-09-25

申请号：US15370570

申请日：2016-12-06

Applicant: ARM Limited

Inventor： Richard F Bryant ,  Max John Batley ,  Lilian Atieno Hutchins ,  Sujat Jamil

IPC: G06F12/12 ,  G06F12/10 ,  G06F12/1036

CPC classification number: G06F12/12 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.

公开(公告)号：US09965399B2

公开(公告)日：2018-05-08

申请号：US15483250

申请日：2017-04-10

Applicant: VMware, Inc.

Inventor： Ole Agesen

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/152 ,  G06F2212/652 ,  G06F2212/68

Abstract: A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.

公开(公告)号：US20180101483A1

公开(公告)日：2018-04-12

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/1045 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128

CPC classification number: G06F12/1054 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G06F2212/652 ,  Y02D10/13

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US20180089102A1

公开(公告)日：2018-03-29

申请号：US15824613

申请日：2017-11-28

Applicant: MIPS Tech, LLC

Inventor： Ranjit J. Rozario ,  Sanjay Patel

IPC: G06F12/1027 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/0844

CPC classification number: G06F12/1027 ,  G06F12/0844 ,  G06F12/1009 ,  G06F12/1054 ,  G06F2212/652 ,  G06F2212/684 ,  Y02D10/13

Abstract: Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

公开(公告)号：US20170315910A1

公开(公告)日：2017-11-02

申请号：US15645819

申请日：2017-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

Abstract: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

公开(公告)号：US20170075582A1

公开(公告)日：2017-03-16

申请号：US14851426

申请日：2015-09-11

Applicant: Red Hat Israel, Ltd.

Inventor： Henri van Riel ,  Michael Tsirkin

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0605 ,  G06F3/0608 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652

Abstract: Methods, systems, and computer program products for receiving a memory access request, the memory access request including a virtual memory address; locating a page entry in a page entry structure, the page entry corresponding to the virtual memory address; identifying that a page corresponding to the page entry includes a sub-page, the sub-page included within a subset of a memory space allocated to the page; determining a page frame number corresponding to the sub-page and an offset corresponding to the sub-page; and accessing the offset within the sub-page.

Abstract translation: 用于接收存储器访问请求的方法，系统和计算机程序产品，所述存储器访问请求包括虚拟存储器地址; 将页面条目定位在页面条目结构中，所述页面条目对应于所述虚拟存储器地址; 识别与所述页面条目相对应的页面包括子页面，所述子页面包括在分配给所述页面的存储器空间的子集内; 确定对应于子页面的页面帧号码和与子页面相对应的偏移量; 并访问子页面中的偏移量。

公开(公告)号：US20170060768A1

公开(公告)日：2017-03-02

申请号：US15013855

申请日：2016-02-02

Applicant: SK Hynix Inc.

Inventor： Fan Zhang ,  Taeil Um ,  Yu Cai

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/652 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: Techniques and systems are provided for tracking commands. Such methods and systems can include maintaining a meta page in a volatile memory to track commands. The meta page can comprise information associated with a non-volatile memory superblock. When an invalidation command is received for a first logical address, the first logical address can be stored along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page.

Abstract translation: 提供了跟踪命令的技术和系统。 这样的方法和系统可以包括将易失性存储器中的元页维护以跟踪命令。 元页面可以包括与非易失性存储器超级块相关联的信息。 当接收到第一逻辑地址的无效命令时，可以在元页中的第一位置中存储第一逻辑地址以及与第一逻辑地址相关联的数据无效的指示。

公开(公告)号：US20170046255A1

公开(公告)日：2017-02-16

申请号：US14824278

申请日：2015-08-12

Applicant: Red Hat Israel, Ltd.

Inventor： Michael Tsirkin

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/652 ,  G06F2212/657

Abstract: Systems and methods for virtual machine based huge page balloon support are provided. A guest operating system (OS) receives a request from a hypervisor for guest memory to be made available to a host operating system (OS). The guest OS further receives a huge page size of a host page and a quantity of requested guest memory. The guest OS then allocates unused guest memory and transmits at least one address of the allocated guest memory to the hypervisor, where the allocated guest memory is a contiguous block of memory that is at least the size of the huge page size and aligned to the size of the huge page size.

Abstract translation: 提供了基于虚拟机的巨大页面气球支持的系统和方法。 客户机操作系统（OS）从来自主机操作系统（OS）的客户机存储器的管理程序接收请求。 客户操作系统进一步收到一个巨大的页面大小的主机页面和一定数量的请求的客户内存。 客户操作系统然后分配未使用的客户端存储器并且将所分配的客户端存储器的至少一个地址发送到虚拟机管理程序，其中所分配的客户端存储器是连续的存储器块，其至少是巨大页面大小的大小并且与尺寸对齐 巨大的页面大小。